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Comparator-multiplexer based 6 bit 1.4GSPS low power ADC 基于6位1.4GSPS低功率ADC的比较器多路复用器
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527793
Saloni, M. Goswami, Babu R. Singh
{"title":"Comparator-multiplexer based 6 bit 1.4GSPS low power ADC","authors":"Saloni, M. Goswami, Babu R. Singh","doi":"10.1109/DTIS.2013.6527793","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527793","url":null,"abstract":"This paper presents a comparator-analog multiplexer based 6 bit analog to digital converter (ADC) using repetitive block of 2*1 multiplexer. The multiplexer is designed using transmission gates while subtractor is designed from a 2 stage op-amp. Such an approach results in high speed and less chip area. The comparator in the proposed work is latch based one making the overall design speed faster. The 6-bit ADC is designed and simulated using MOSIS (AMIS) C5X design kit with 2.5 V supply. The proposed design achieves a maximum speed of 1.4 GSPS and dissipates 14.1 mW of power with INL of 0.43 LSB, DNL of 0.38 LSB, SNR of 35.47 dB and SNDR of 34.29 dB respectively.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116127324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact modeling and applications of Carbon nanotube field effect transistors CNTFETs based CMOS-like complementary NOR, OR, NAND, and AND logic gates 碳纳米管场效应晶体管(cntfet)的紧凑建模和应用，基于类似cmos的互补NOR, OR, NAND和and逻辑门
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527803
Lobna I'Msaddak, D. B. Issa, A. Kachouri
{"title":"Compact modeling and applications of Carbon nanotube field effect transistors CNTFETs based CMOS-like complementary NOR, OR, NAND, and AND logic gates","authors":"Lobna I'Msaddak, D. B. Issa, A. Kachouri","doi":"10.1109/DTIS.2013.6527803","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527803","url":null,"abstract":"In this paper, CMOS architectures for NOT, AND, OR, NOR and NAND gates were proposed using C-CNTFETs and their operational characteristics were checked using the simulator SPICE. The CNTFETs utilize a semiconducting Carbon nanotube (CNT) channel controlled by isolated electrostatic gates. Circuit-compatible model of conventional CNTFET, which demonstrates p-type or n-type switching behavior depending on the gate voltage, is implemented in SPICE and the designs are extensively simulated in SPICE. The power and delay performance of CNTFETs were investigated in basic logic gates for DCNT=1.42 nm on this SPICE model.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
From system model formalization towards correct and efficient HW/SW design 从系统模型形式化到正确高效的软硬件设计
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527784
Mohamad Jaber, A. Chagoya-Garzon, F. Rousseau
{"title":"From system model formalization towards correct and efficient HW/SW design","authors":"Mohamad Jaber, A. Chagoya-Garzon, F. Rousseau","doi":"10.1109/DTIS.2013.6527784","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527784","url":null,"abstract":"We propose a formalism including a set of constraints for the modeling of a correct and efficient HW/SW systems. The hardware architecture is described as the interconnection of several heterogeneous MPSoCs (called tiles). The presented formalism encompasses all known tiles. The software model is described as a kahn process network. Using a dedicated framework, we define a domain language targeting the proposed formalism along with its constraints. The goal is to specify a (1) correct hardware architecture, (2) correct software model, and (3) correct mapping which binds a software model on a hardware architecture. Finally, we show the possibility to automatically construct a set of complete models from a partial one, where the constructed models satisfy the set of the predefined constraints.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122036104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multivariate statistical techniques for analog parametric test metrics estimation 模拟参数测试度量估计的多元统计技术
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527768
K. Huang, H. Stratigopoulos, L. Abdallah, S. Mir, A. Bounceur
{"title":"Multivariate statistical techniques for analog parametric test metrics estimation","authors":"K. Huang, H. Stratigopoulos, L. Abdallah, S. Mir, A. Bounceur","doi":"10.1109/DTIS.2013.6527768","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527768","url":null,"abstract":"The high cost for testing the analog blocks of a modern chip has sparked research efforts to replace the standard tests with less costly alternative tests. However, test engineers are rather reluctant to adopt alternative tests unless they are evaluated thoroughly before moving to production and they are proven to maintain test quality. This paper gives a comprehensive overview of statistical techniques based on density estimation for evaluating analog parametric test metrics during the test development phase. A large-scale simulation study is carried out for the first time with the aim to demonstrate these techniques in action.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126193535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Electrical characteristics of graphene wrinkles extracted by conductive Atomic Force Microscopy and electrical measurements on kelvin structures 导电原子力显微镜提取石墨烯皱纹的电学特性和开尔文结构的电学测量
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527806
Omar Alnemer, Helmy Ally, Aamna Alshehhi, I. Saadat, T. Souier, A. Gougam, H. Nayfeh
{"title":"Electrical characteristics of graphene wrinkles extracted by conductive Atomic Force Microscopy and electrical measurements on kelvin structures","authors":"Omar Alnemer, Helmy Ally, Aamna Alshehhi, I. Saadat, T. Souier, A. Gougam, H. Nayfeh","doi":"10.1109/DTIS.2013.6527806","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527806","url":null,"abstract":"One of the key deliverables of using graphene as a channel in transistors is to achieve low source and drain parasitic contact resistance. Careful characterization of the surface of graphene is needed in order to improve understanding of the metal to graphene interface. In this paper, we employ conductive Atomic Force Microscope (C-AFM) to characterize the electrical properties of these wrinkles as a function of the applied force. At low forces, the wrinkles are more conductive than flat regions and at high forces the wrinkles have similar conductance as the flat regions. Graphene devices were fabricated and the total resistance of graphene in these devices was measured to be in the range 2Ω to 10MΩ. Additional research is planned to investigate if the wrinkles impact the electrical contact resistance of large area structures.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131438992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing 利用多vdd、多vth和栅极尺寸的高性能超低功耗DFT自下而上设计
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527804
M. Jafari, M. Imani, M. Fathipour, Nader Sehatbakhsh
{"title":"Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing","authors":"M. Jafari, M. Imani, M. Fathipour, Nader Sehatbakhsh","doi":"10.1109/DTIS.2013.6527804","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527804","url":null,"abstract":"This paper focuses on the design of an FFT based on butterfly blocks. FFT algorithm is Radix-2 Decimation in Frequency and implementation is done in fixed point using MATLAB software. The low power characteristics of proposed design is achieved using power gating for switching off the non-critical path multipliers in off periods and holding their output nodes in their previous values. This improves the leakage of the circuit effectively while does not affect the performance. Making all path delays equal to the highest path delay improves the energy consumption without any performance penalty. Another mode of operation is high performance mode which employs low-VT transistors especially in critical path and high-VT transistors in other paths. MATLAB Simulations confirms precision of the design. Finally SNR is found for fixed point and floating point versus word width and number of points of FFT.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"401 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126672905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Transfer-free grown bilayer graphene memory devices 无转移生长双层石墨烯存储器件
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527769
P. Wessely, U. Schwalke
{"title":"Transfer-free grown bilayer graphene memory devices","authors":"P. Wessely, U. Schwalke","doi":"10.1109/DTIS.2013.6527769","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527769","url":null,"abstract":"In this paper we report on the application of in-situ CCVD grown bilayer graphene field effect transistors (BiLGFETs) as memory devices, grown in a Silicon-CMOS compatible fabrication process. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1×105 and 1×107 at room temperature [1, 2]. The hysteresis of BiLGFETs depends on the cycling range of the applied backgate voltage VBG while the sub-threshold slope is uniform for varied temperatures and varied cycling ranges of the backgate voltage [3]. Based on the observed properties of BiLGFETs it is possible to use BiLGFETS as memory devices.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114873350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy efficient and hign bandwidth embedded memory implementation 节能和高带宽嵌入式存储器的实现
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527790
B. Mohammad, H. Saleh
{"title":"Energy efficient and hign bandwidth embedded memory implementation","authors":"B. Mohammad, H. Saleh","doi":"10.1109/DTIS.2013.6527790","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527790","url":null,"abstract":"Embedded memory is an important part of processors and system on Chip main matrix (performance, power and area). As a result, the ever increasing integration of embedded memory continues. SRAM cell is the preferred option for embedded memory because of low power density, smaller area, layout regularity, and high performance. Implementation options and organization of such memory have big impact on the power, area, and performance. The goal of this paper is to analyze the different options available for SRAM to enable energy efficient implementation including low voltage operation. The paper will present the findings of implementing high bandwidth (256-bit) L1 cache using SRAM cell with full swing bitline using 28nm foundry process technology. The result shows the design with full swing is more power efficient (10% less array power) than small swing sense amplifier based scheme. The area for the two design are compatible with 4-5% more area overhead for full swing. The proposed design support wordline overdrive assist circuit during write access to enable low voltage operation.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125346968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors NBTI效应对PMOS晶体管阈值电压退化率的自影响
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527796
B. Eghbalkhah, S. Gharavi, A. Afzali-Kusha, M. Ghaznavi-Ghoushchi
{"title":"Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors","authors":"B. Eghbalkhah, S. Gharavi, A. Afzali-Kusha, M. Ghaznavi-Ghoushchi","doi":"10.1109/DTIS.2013.6527796","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527796","url":null,"abstract":"Reliability aware circuit design and estimation of circuit performance during lifetime is a critical challenge in design and test of integrated circuits in nanometer technology nodes. Negative Bias Temperature Instability (NBTI) as the most dominant aging source is deeply dependent on the operating temperature of the circuit. In this work, we have developed a simulation framework to dynamically estimate the effect of NBTI on power consumption of the circuit and consequently the operating temperature. The effect of NBTI on temperature will act as a natural negative feedback mechanism to reduce the degradation rate of threshold voltage (Vth). Simulation results show that estimated degradation in Vth is about 4.1% less than the predicted amount by current models.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126767390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures 分析了核心单元和感测放大器中并发可变性对SRAM读存取失败的影响
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527775
E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine
{"title":"Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures","authors":"E. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine","doi":"10.1109/DTIS.2013.6527775","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527775","url":null,"abstract":"Conventionally, the access failures in SRAMs are treated at core cell level by means of differential bit line voltage analysis. In this work it is shown that under the assumption of random process variability, the conventional approach no longer suffices. It still holds that the differential bit line voltage is degraded by the variability in core cell transistors, but the way this voltage difference is interpreted by the sense amplifier to complete the read operation is influenced by random variability affecting its transistors. Case studies show how variability affecting the sense amplifier can degrade or improve its ability to read the data stored by the core cell, which is itself affected by variability. Using principal component analysis and the SB-SI method, we performed a parametric analysis of the sense amplifier/core cell system and we evaluated the joint probability of access failure. A three times increase in the failure probability has been observed when compared to cell's failure probability. Also, the minimum variability value for which a failure is observed is ~2.5X smaller when joint variability is assumed compared to the case when only the core cell is affected by variability.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128386876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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