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Monitoring operating temperature and supply voltage in achieving high system dependability 监测工作温度和供电电压，实现系统的高可靠性
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527788
Muhammad Aamir Khan, H. Kerkhoff
{"title":"Monitoring operating temperature and supply voltage in achieving high system dependability","authors":"Muhammad Aamir Khan, H. Kerkhoff","doi":"10.1109/DTIS.2013.6527788","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527788","url":null,"abstract":"System dependability being a set of number of attributes, of which the important reliability, heavily depends on operating temperature and supply voltage. Any change beyond the designed specifications may change the system performance and could result in system reliability and hence dependability problems. These reliability problems could be short-term variations and can be solved if the system returns back to its normal operational temperature and supply voltage. Therefore, these reliability problems should be differentiated from the other long-term reliability problems resulting from aging mechanisms. These are a function of stress time and have a cumulative nature. This differentiation is essential to better manage the system dependability during its operational life. This separation of two reliability problems requires a regular monitoring of the system operating temperature and the supply voltage during its operational life. The problem has been solved in the proposed hardware architecture and workflow that takes this monitoring into account to tackle them separately and carries out proper actions in order to enhance the system dependability. The simulation results for a target system carried out in LabVIEW environment fully support the proposed idea.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128375770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Privilege escalation attack through address space identifier corruption in untrusted modern processors 在不可信的现代处理器中通过地址空间标识符损坏进行特权升级攻击
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527798
M. Maniatakos
{"title":"Privilege escalation attack through address space identifier corruption in untrusted modern processors","authors":"M. Maniatakos","doi":"10.1109/DTIS.2013.6527798","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527798","url":null,"abstract":"Privilege escalation attacks are one of the major threats jeopardizing microprocessor operation. Such attacks aim to maliciously increase the privilege level of the executed process, in order to access unauthorized resources. Modern microprocessors include complex memory management modules, with various different privilege levels and numerous ways to change the privilege level. In this paper, we present a malicious modification in the microprocessor process switch mechanism. Contrary to recent work presented in literature, the modification can be deployed during manufacturing process, as it consists of a trivial addition of a gate or wire sizing. The minimal footprint, however, comes at the cost of small window of attack opportunities. Experimental results show that a modification-aware application can gain escalated privileges within a few thousand clock cycles. Moreover, the malicious code has been added to SPEC benchmarks, and we show that the modified benchmarks can get escalated privileges before the end of typical workload, with minimal performance overhead.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124486352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Lightweight cipher implementations on embedded processors 嵌入式处理器上的轻量级密码实现
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527783
Sagar Khurana, Souvik Kolay, C. Rebeiro, Debdeep Mukhopadhyay
{"title":"Lightweight cipher implementations on embedded processors","authors":"Sagar Khurana, Souvik Kolay, C. Rebeiro, Debdeep Mukhopadhyay","doi":"10.1109/DTIS.2013.6527783","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527783","url":null,"abstract":"“Internet on things” is a growing trend towards connecting every electronic device to each other. In one end of the communication, there are sensor nodes, which would generally be power and resource constrained. On the other end, there are more complex base systems, which will accumulate information from multiple sensors. This communication may comprise of sensitive information, which brings the need of a secure communication protocol. Lightweight ciphers have to be used due to the presence of the resource constraint sensors. The standard lightweight ciphers are hardware friendly but can be slow in software. This can hinder the performance in the base systems which are generally built with microprocessors. Hardware-software co-design can be used to improve the performance. In this paper, we show that the performance of a standard lightweight block cipher like Present can be improved by having specific instructions for bit permutation; a vital component in modern lightweight block ciphers. We show experimentally the performance benefits by adding bit permutation instructions for the NIOS II processor.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131263469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM 具有改进的读写SNM的32kb 90nm 9t细胞亚阈值SRAM
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527787
M. Zamani, Sina Hassanzadeh, K. Hajsadeghi, R. Saeidi
{"title":"A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM","authors":"M. Zamani, Sina Hassanzadeh, K. Hajsadeghi, R. Saeidi","doi":"10.1109/DTIS.2013.6527787","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527787","url":null,"abstract":"The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense amplifier to easily read the bitline current. The 0.3V sub-threshold SRAM post-layout simulation using 90nm TSMC CMOS model confirms the proposed 32k SRAM performance.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"580 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114058412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Embedding test vectors in accumulator - based TPG using progressive search 用渐进式搜索方法在基于累加器的TPG中嵌入测试向量
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527800
I. Voyiatzis, C. Efstathiou, C. Sgouropoulou
{"title":"Embedding test vectors in accumulator - based TPG using progressive search","authors":"I. Voyiatzis, C. Efstathiou, C. Sgouropoulou","doi":"10.1109/DTIS.2013.6527800","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527800","url":null,"abstract":"In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(k), where k is an arbitrarily small constant. Comparisons with previously proposed schemes indicate that the proposed method results in lower test application time.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127837599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Capturing and mitigating the NBTI effect during the design flow for extensible processors 在可扩展处理器的设计流程中捕获和减轻NBTI效应
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527785
M. Kamal, A. Afzali-Kusha, S. Safari, M. Pedram, B. Eghbalkhah
{"title":"Capturing and mitigating the NBTI effect during the design flow for extensible processors","authors":"M. Kamal, A. Afzali-Kusha, S. Safari, M. Pedram, B. Eghbalkhah","doi":"10.1109/DTIS.2013.6527785","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527785","url":null,"abstract":"This paper studies the impact of the delay degradation arising from the Negative Bias Temperature Instability (NTBI) effect on the extended instruction set architecture (ISA) and the ALU design of extensible processors. In particular, the NBTI delay degradation on the performance of extensible processors is modeled during the conventional design flow. While the results of this study show that, in some cases, the lifetime of the extensible processors is decreased, in most cases, the extended ISA is able to improve the lifetime compared to the baseline processor. Next, three different design flows are presented to lower the NBTI effect. These flows are based on reducing the stress on custom instructions (CIs) by considering the number of occurrences of the selected CIs in the data flow graph of the target application and by pruning the CIs whose NBTI-induced delay degradations are large and result in slow down of the extensible processor. Experimental results assess the effectiveness of the proposed methods.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116296789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Statistical modelling of analog circuits for test metrics computation 测试度量计算用模拟电路的统计建模
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527772
Kamel Beznia, A. Bounceur, S. Mir, R. Euler
{"title":"Statistical modelling of analog circuits for test metrics computation","authors":"Kamel Beznia, A. Bounceur, S. Mir, R. Euler","doi":"10.1109/DTIS.2013.6527772","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527772","url":null,"abstract":"Analog Built-In Test (BIT) techniques should be evaluated at the design stage, before the real production, by estimating the analog test metrics, namely Test Escapes (TE) and Yield Loss (YL). Due to the lack of comprehensive fault models, these test metrics are estimated under process variations. In this paper, we estimate the joint cumulative distribution function (CDF) of the output parameters of a Circuit Under Test (CUT) from an initial small sample of devices obtained from Monte Carlo circuit simulation. We next compute the test metrics in ppm (parts-per-million) directly from this model, without sampling the density as in previous works. The test metrics are obtained very fast since the computation does not depend on the size of the output parameter space and there is no need for density sampling. An RF LNA modeled with a Gaussian copula is used to compare the results with past approaches.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125755921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high-throughput, contention-free low-power, Radix-2 1k,2k, 4k and 8k-point fast fourier transform engine using 28nm standard-cell process 采用28nm标准单元工艺的高通量、无争用、低功耗、Radix-2 1k、2k、4k和8k点快速傅立叶变换引擎
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527807
H. Saleh, B. Mohammad, Maher Maalouf
{"title":"A high-throughput, contention-free low-power, Radix-2 1k,2k, 4k and 8k-point fast fourier transform engine using 28nm standard-cell process","authors":"H. Saleh, B. Mohammad, Maher Maalouf","doi":"10.1109/DTIS.2013.6527807","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527807","url":null,"abstract":"This paper presents a high-throughput, contention-free, low-power, Radix-2 decimation in frequency fast Fourier transform core implemented in 28nm industry representative standard-cell process. It utilizes an algorithm to eliminate memory access contention and maximize throughput by eliminating bubbles in the butterfly's pipeline. The implementation of the FFT core is presented, including timing and place-and-route result in 28nm standard CMOS process. The FFT core can perform 1024, 2048, 4096 and 8192 points FFT. The FFT core uses two-port SRAM elements and achieves a throughput of 2-butterfly operations every clock cycle. The FFT core performs 8K-points FFT in around 40uS.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"594 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Preliminary all digital Channel Filter design for LTE-Advanced software radio implementation LTE-Advanced软件无线电实现的全数字信道滤波器初步设计
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527802
M. Hallal, Bassam Swaked, L. Albasha
{"title":"Preliminary all digital Channel Filter design for LTE-Advanced software radio implementation","authors":"M. Hallal, Bassam Swaked, L. Albasha","doi":"10.1109/DTIS.2013.6527802","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527802","url":null,"abstract":"This paper introduces a preliminary Tunable Digital Low pass Channel Filter designed and implemented according to the 3GPP Release 10 Receiver Characteristics. The filter is built using Altera's DSP Builder Design Environment and Matlab Simulink to allow for FPGA implementation at a later stage. The functional simulation shows that the filter can satisfy Release 10 requirements in terms of magnitude response. This filter is scheduled for implementation on one of Altera's FPGAs in order to assess its performance.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134512191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new cross contamination aware routing method with intelligent path exploration in digital microfluidic biochips 基于智能路径探索的数字微流控生物芯片交叉污染感知路由新方法
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527777
P. Roy, Pampa Howladar, Rupam Bhattacharjee, H. Rahaman, P. Dasgupta
{"title":"A new cross contamination aware routing method with intelligent path exploration in digital microfluidic biochips","authors":"P. Roy, Pampa Howladar, Rupam Bhattacharjee, H. Rahaman, P. Dasgupta","doi":"10.1109/DTIS.2013.6527777","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527777","url":null,"abstract":"Digital microfluidic systems in recent years have been developed as an alternative platform for execution of multiple conventional laboratory methods simultaneously on a single planar 2D array of electrodes targeted for biochemical analysis and biomedical applications. Due to its discrete nature droplets can be manipulated through multiple reconfigurable paths derived by preprogrammed electrode actuation sequences through this planar array known as digital microfluidic biochip system. Cross contamination between heterogeneous samples turns out to be a major issue concerned with transportation of droplets and correctness of the detection results for the bioassay protocols -which is highly significant for clinical diagnostics and toxicity monitoring applications. In this paper we have proposed an intelligent route path exploration technique that attempts partially or completely to avoid the number of cross contamination depending on the fluidic constraints employed during routing. The path is further refined using intelligent detour by identifying zones of friction between two adjacent route paths that optimizes the overall route time by reducing the overall time for stalling while routing -as well as further optimization of resources to be utilized. The simulation is carried out on test benches of benchmark suite I and benchmark suite III. The results show improvement in overall as well as average route time and major reduction in the number of crossovers.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130245988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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