发布求助
文献互助 智能选刊 最新文献

2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)最新文献

筛选
英文 中文
Reversible logic implementation of AES algorithm AES算法的可逆逻辑实现
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527794
K. Datta, Vishal Shrivastav, I. Sengupta, H. Rahaman
{"title":"Reversible logic implementation of AES algorithm","authors":"K. Datta, Vishal Shrivastav, I. Sengupta, H. Rahaman","doi":"10.1109/DTIS.2013.6527794","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527794","url":null,"abstract":"Since the selection of the Rijndael cryptosystem as a new Advanced Encryption Standard (AES) in 2000, many hardware implementations of AES have been reported. Some of these implementations are optimized for speed, some for area, some for reconfigurability, and some for low-power applications. Again, reversible logic synthesis methodologies have drawn the attention of researchers in recent times, mainly with the prospect of quantum computing becoming a reality, and the potential of reversible logic circuits for providing ultra low-power implementations. Although many of the cryptographic primitives are inherently reversible by nature, very little work has been done towards reversible logic implementations of the same. The only published works relate to reversible implementations of Montgomery multiplication algorithm, which has applications in cryptography. The present paper, possibly for the first time, presents a reversible logic implementation of a block cipher, namely, 128-bit AES. The various AES functional blocks have been synthesized using reversible gates, using which an overall reversible architecture has been proposed. The pipelined version as suggested can only be used in the Electronic Code Book (ECB) mode. The hardware complexity of the implementation has been evaluated using the number of reversible gates required and the quantum cost.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115118464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 10MHz CTDSM with differential VCO-based quantizer in 90nm 基于差分vco量化器的90nm 10MHz CTDSM
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527792
B. Yousefzadeh, A. Hajian, M. Sharifkhani
{"title":"A 10MHz CTDSM with differential VCO-based quantizer in 90nm","authors":"B. Yousefzadeh, A. Hajian, M. Sharifkhani","doi":"10.1109/DTIS.2013.6527792","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527792","url":null,"abstract":"This paper presents a new architecture for VCO-based Continuous Time Delta Sigma Modulators. This approach is based on the differential configuration for the quantizer while maintains its inherent dynamic element matching property. Consuming no additional power and area compared to the conventional scheme, this architecture can eliminate the even orders of harmonic distortion and achieve higher linearity. Theoretical analysis for signal to quantization noise, power and area consumption and mismatch effect is provided. To illustrate the effectiveness of the new architecture in continuous time modulators, a modulator with 640 MHz sampling rate utilizing the mentioned quantizer is simulated in 90nm technology. Obtaining linearity enhancement compared to the conventional design, the modulator achieves the maximum SNDR of 72dB over a 10 MHz bandwidth. The modulator consumes 56.9 mW from a 1.2 V supply.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125719305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-CNTFETs for power device applications: Investigation of CCVD grown CNTs by means of atomic force microscopy 用于功率器件的多cntfet:用原子力显微镜研究CCVD生长的cnt
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527767
Martin Keyn, U. Schwalke
{"title":"Multi-CNTFETs for power device applications: Investigation of CCVD grown CNTs by means of atomic force microscopy","authors":"Martin Keyn, U. Schwalke","doi":"10.1109/DTIS.2013.6527767","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527767","url":null,"abstract":"In this work we use atomic force microscopy to explore carbon nanotubes (CNTs) which are grown by means of catalytic chemical vapor deposition (CCVD). The used process can be utilized to fabricate hundreds of carbon nanotube field-effect transistors (CNTFETs) for logic as well as for power device applications. The application type is selected through specially patterned source/drain contacts which either allow only one linking CNT (logic applications) or provide large scale parallelization of numerous CNTs (“multi-CNTFET”) for power device applications.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131648380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Symmetric transparent online BIST for arrays of word-organized RAMs 用于字组织ram数组的对称透明在线BIST
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527791
I. Voyiatzis, C. Efstathiou, C. Sgouropoulou
{"title":"Symmetric transparent online BIST for arrays of word-organized RAMs","authors":"I. Voyiatzis, C. Efstathiou, C. Sgouropoulou","doi":"10.1109/DTIS.2013.6527791","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527791","url":null,"abstract":"Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. Previous works on symmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach, given the large number of memories available in current chips, increases the hardware overhead of the BIST circuitry. In this work we propose a Symmetric transparent BIST scheme that can be utilized to test RAMs of different word widths; hence, more than one RAMs can be tested in a roving manner. The hardware overhead of the proposed scheme is considerably smaller compared to the utilization of previously proposed symmetric transparent schemes, for typical memory configurations.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New CMOS realization of Z Copy Voltage Differencing Buffered Amplifier and its current-mode filter application Z拷贝压差缓冲放大器的新型CMOS实现及其电流型滤波器的应用
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527780
Arda Guney, Ersin Alaybeyoğlu, H. Kuntman
{"title":"New CMOS realization of Z Copy Voltage Differencing Buffered Amplifier and its current-mode filter application","authors":"Arda Guney, Ersin Alaybeyoğlu, H. Kuntman","doi":"10.1109/DTIS.2013.6527780","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527780","url":null,"abstract":"In this paper, a new CMOS realization of Z Copy Voltage Differencing Buffered Amplifier (ZC-VDBA) is presented. The performance of the proposed circuit is demonstrated on a new current-mode Kerwin-Huelsman-Newcomb (KHN) filter application, employing two ZC-VDBAs and two grounded capacitors. The circuit simulations are verified using BSIM3 0.18 μm level-7 SPICE parameters.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127902730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
RF energy harvesting for autonomous wireless sensor networks 自主无线传感器网络的射频能量采集
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527782
M. Al-Ali, L. Albasha, N. Qaddoumi
{"title":"RF energy harvesting for autonomous wireless sensor networks","authors":"M. Al-Ali, L. Albasha, N. Qaddoumi","doi":"10.1109/DTIS.2013.6527782","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527782","url":null,"abstract":"The system specifications of RF energy harvesting are outlined, indicating the general guideline of low power circuit and system design as well as the frequency set to be used in the system. Four frequency bands representing five wireless standards were chosen namely, GSM, DTV, Wi-Fi, Bluetooth and road tolling system. A harvesting system has been designed and simulated. A microstrip line antenna, RF-DC rectifier circuit and a voltage doubler circuit were designed. The simulations show promising preliminary results for the RF energy harvesting system compared to similar work in literature.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A fully integrated linear CMOS power amplifier with high output power and dynamic range for WiMAX application 完全集成的线性CMOS功率放大器，具有高输出功率和动态范围，适用于WiMAX应用
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527773
A. R. Belabad, N. Masoumi, Shahin Jafarabadi-Ashtiani, Nader Sehatbakhsh
{"title":"A fully integrated linear CMOS power amplifier with high output power and dynamic range for WiMAX application","authors":"A. R. Belabad, N. Masoumi, Shahin Jafarabadi-Ashtiani, Nader Sehatbakhsh","doi":"10.1109/DTIS.2013.6527773","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527773","url":null,"abstract":"A fully integrated 2.4 GHz power amplifier with high output power in a standard 0.18 μm CMOS process for WiMAX application is presented. For increasing linearity and efficiency, a parallel cascade class A&B power amplifier is used. A new interleaved PCT power combiner is proposed for increasing output power that combines output current of two similar power amplifiers. The proposed power amplifier with 3.3 V power supply provides maximum output power of 32.5 dBm and power added efficiency of 37.9% at 2.4 GHz operating frequency. The proposed power amplifier exhibits high output power of 32.2 dBm at 1dB compression point. The simulation results for proposed PA with modulated OFDM signal show that -31 dB error vector magnitude at the average power of 25 dBm can be achieved.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117324868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Robust polysilicon gate FinFET SRAM design using dynamic back-gate bias 基于动态后门偏置的稳健多晶硅栅极FinFET SRAM设计
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527801
B. Ebrahimi, A. Afzali-Kusha, Nader Sehatbakhsh
{"title":"Robust polysilicon gate FinFET SRAM design using dynamic back-gate bias","authors":"B. Ebrahimi, A. Afzali-Kusha, Nader Sehatbakhsh","doi":"10.1109/DTIS.2013.6527801","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527801","url":null,"abstract":"In this paper, polysilicon gate FinFET SRAM back-gate design is investigated. First, a previous approach for increasing the read stability is revisited and a device approach is proposed to alleviate the increased access time. Second, a dynamic back-gate design for pull up transistors is presented. In this design, the proposed circuitry can be shared for each row or column, so its area penalty is negligible.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116467933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA implementation of genetic algorithm for dynamic filter-bank-based multicarrier systems 基于动态滤波器组的多载波系统遗传算法的FPGA实现
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527781
Nader Sehatbakhsh, M. Aliasgari, S. M. Fakhraie
{"title":"FPGA implementation of genetic algorithm for dynamic filter-bank-based multicarrier systems","authors":"Nader Sehatbakhsh, M. Aliasgari, S. M. Fakhraie","doi":"10.1109/DTIS.2013.6527781","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527781","url":null,"abstract":"This paper presents FPGA implementation of a genetic algorithm based canonical signed digit (CSD) synthesizer for a dynamic filter-bank-based multicarrier system which employs a regular prototype filter with a certain specification. Using Genetic Algorithm, the proposed system searches for the best coefficients of prototype filter in CSD format for the filter bank based multicarrier (FBMC) system. The system is reconfigurable so that filter characteristics (number of coefficients) and their precisions (number of bits) for each coefficient can be set dynamically. Finally, the design is entirely implemented on a field programmable gate array (FPGA) chip. Simulations and synthesis results are obtained to show the merit of the proposed design. Results demonstrate that the system needs less than one second to provide desired filter coefficients when a prototype filter with 64 coefficients is employed.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"45 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116021360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel low power 8T-cell sub-threshold SRAM with improved read-SNM 一种新型低功耗8t单元亚阈值SRAM，具有改进的读- snm
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527774
Sina Hassanzadeh, M. Zamani, K. Hajsadeghi, R. Saeidi
{"title":"A novel low power 8T-cell sub-threshold SRAM with improved read-SNM","authors":"Sina Hassanzadeh, M. Zamani, K. Hajsadeghi, R. Saeidi","doi":"10.1109/DTIS.2013.6527774","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527774","url":null,"abstract":"The fast growth of battery-operated portable applications has compelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the sub-threshold regime many structures has been proposed adding extra transistors to the conventional 6T-cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is simple. The new structure uses fewer controlling signal in comparison to the conventional 8T-cell SRAM. Thus, the proposed 32k SRAM consumes 25% lower power consumption in the read operation for 0.3V sub-threshold SRAM in 90nm TSMC CMOS model.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124055788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书