Capturing and mitigating the NBTI effect during the design flow for extensible processors

Abstract

This paper studies the impact of the delay degradation arising from the Negative Bias Temperature Instability (NTBI) effect on the extended instruction set architecture (ISA) and the ALU design of extensible processors. In particular, the NBTI delay degradation on the performance of extensible processors is modeled during the conventional design flow. While the results of this study show that, in some cases, the lifetime of the extensible processors is decreased, in most cases, the extended ISA is able to improve the lifetime compared to the baseline processor. Next, three different design flows are presented to lower the NBTI effect. These flows are based on reducing the stress on custom instructions (CIs) by considering the number of occurrences of the selected CIs in the data flow graph of the target application and by pruning the CIs whose NBTI-induced delay degradations are large and result in slow down of the extensible processor. Experimental results assess the effectiveness of the proposed methods.