Comparator-multiplexer based 6 bit 1.4GSPS low power ADC

Abstract

This paper presents a comparator-analog multiplexer based 6 bit analog to digital converter (ADC) using repetitive block of 2*1 multiplexer. The multiplexer is designed using transmission gates while subtractor is designed from a 2 stage op-amp. Such an approach results in high speed and less chip area. The comparator in the proposed work is latch based one making the overall design speed faster. The 6-bit ADC is designed and simulated using MOSIS (AMIS) C5X design kit with 2.5 V supply. The proposed design achieves a maximum speed of 1.4 GSPS and dissipates 14.1 mW of power with INL of 0.43 LSB, DNL of 0.38 LSB, SNR of 35.47 dB and SNDR of 34.29 dB respectively.