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2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)最新文献

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Reconfigurable low noise amplifier using MEMS varactor 使用MEMS变容管的可重构低噪声放大器
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527795
N. Emami, Omer Arshed, M. Bakri-Kassem, L. Albasha
{"title":"Reconfigurable low noise amplifier using MEMS varactor","authors":"N. Emami, Omer Arshed, M. Bakri-Kassem, L. Albasha","doi":"10.1109/DTIS.2013.6527795","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527795","url":null,"abstract":"A frequency reconfigurable LNA is designed using novel tunable RF-MEMS varactors. The designed MEMS varactor can be fabricated and integrated in 0.35μm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). The frequency of operation of the LNA varies from 2.7 GHz to 3.1 GHz by tuning the capacitance of the MEMS varactor. The MEMS varactor is simulated in ANSYS and the obtained results are included in the LNA design. The LNA performance is simulated and the results are discussed.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125033556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low noise high frequency CNTFET amplifier 低噪声高频CNTFET放大器
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527776
Wafa Makni, I. Barrage, H. Samet, M. Masmoudi, Montasar Najari
{"title":"Low noise high frequency CNTFET amplifier","authors":"Wafa Makni, I. Barrage, H. Samet, M. Masmoudi, Montasar Najari","doi":"10.1109/DTIS.2013.6527776","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527776","url":null,"abstract":"This paper focuses on performance challenges related to Mos-based systems operating on high frequency ranges. One solution for this issue is to use carbon nanotube transistor (CNTFET) because of their promising performances. Therefore, to improve the device performance at high frequency ranges, designers must reduce the parasitic capacitances by using an array of parallel nanotubes as the transistor channel. This work presents the simulation of low noise amplifier using CNTFET technology. At 165GHz, the LNA simulation results show a power gain of 16dB, a noise figure of 0.25dB and very low power consumption equal to 0.47mW.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Continuous and automatic charging and discharging for lithium-ion batteries 锂离子电池连续自动充放电
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527789
Yahya Al-Khawam, L. Albasha, Noor Al-khawam
{"title":"Continuous and automatic charging and discharging for lithium-ion batteries","authors":"Yahya Al-Khawam, L. Albasha, Noor Al-khawam","doi":"10.1109/DTIS.2013.6527789","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527789","url":null,"abstract":"This paper introduces another methodology of charging lithium-ion batteries for portable devices such as laptops and tablets. The presented low-cost charger circuit which is developed to be easily designed follows the constant-current and constant-voltage scheme, CC-CV. Also, this charger circuit will continuously and automatically charge and discharge the battery in order to protect it from over-charging and over-discharging and so maintain its life cycle.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126351742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-dissipation comparison of two dependability approaches for multi-processor systems 多处理器系统两种可靠性方法的功耗比较
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527778
Yong Zhao, Xiao Zhang, H. Kerkhoff
{"title":"Power-dissipation comparison of two dependability approaches for multi-processor systems","authors":"Yong Zhao, Xiao Zhang, H. Kerkhoff","doi":"10.1109/DTIS.2013.6527778","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527778","url":null,"abstract":"The additional power dissipation involved in introducing a high dependability in multi-processor systems is nowadays becoming a major concern (power-aware dependability). In this paper, the power dissipation components of a recently implemented scan-test based dependability testing approach for a multi-processor Systems-on-Chip (SoC) is evaluated. It is shown that the application of scan-test vectors to the cores is the major power contributor. To avoid this dissipation and hence scan test, a new prognostic approach for life-time prediction using on-line health monitors is proposed accomplishing the same high dependability. It will be shown that the latter approach consumes less power under the same dependability specifications. Actual measurements and theoretical calculations are provided as well as a suggestion for future dependable systems given.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126190512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of an ultra-low power 32-bit adder operating at subthreshold voltages in 45-nm FinFET 45纳米FinFET超低功耗32位加法器的亚阈值电压设计
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527799
M. Jafari, M. Imani, Mohammad Ansari, M. Fathipour, Nader Sehatbakhsh
{"title":"Design of an ultra-low power 32-bit adder operating at subthreshold voltages in 45-nm FinFET","authors":"M. Jafari, M. Imani, Mohammad Ansari, M. Fathipour, Nader Sehatbakhsh","doi":"10.1109/DTIS.2013.6527799","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527799","url":null,"abstract":"This paper describes the design of an ultimately low power subthreshold 32-bit adder, implemented in 45-nm technology. Low power design is achieved by using FinFET devices which are nowadays a basic component of very scaled and low power circuits. The circuit was tested in all corners and its consumption is as low as 10fJ per computation with 0.4V supply voltage and maximum operating frequency about 260KHz. A very alluring feature of this design is that it could be speed up to 256MHz in 1.13V supply voltage and consuming only 59.05fJ energy per calculation. Another appealing feature of propose design is its stable and reliable operation with 130mV supply voltage by 3.74 KHz operation frequency. In this mode the design consumes only 43.77fW. This multi-mode design could be used in integrated circuit design which uses power management technique to reduce energy consumption by OS software job assignment. The simulations were done by HSPISE 2008.all model are extracted from FinFET 45nm PTM library.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129589155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Coupled mode analysis of integrated optical waveguide array sensors 集成光波导阵列传感器的耦合模式分析
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527797
S. Serunjogi, Jaime Viegas
{"title":"Coupled mode analysis of integrated optical waveguide array sensors","authors":"S. Serunjogi, Jaime Viegas","doi":"10.1109/DTIS.2013.6527797","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527797","url":null,"abstract":"In this paper, we propose and model an improved integrated optical waveguide array refractive index sensor, using coupled mode theory and the effective index approximation method. These devices can be used in integrated physicochemical sensing applications, by judicious selection of cladding transducer materials that convert variations in chemical composition into changes of refractive index. We demonstrate that a linear array of multiple co-planar waveguides retains the imaging characteristics of current Multimode Interference (MMI) sensors but with improved device footprint (by decreasing the effective beat length of the device), and higher sensitivity, by increasing the active surface area that is critical in enhancing the detection limit in biological and chemical sensors.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132551476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy efficient system-on-chip architecture for non-invasive mobile monitoring of diabetics 用于糖尿病患者无创移动监测的高能效芯片系统架构
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527805
M. Alhawari, A. Khandoker, B. Mohammad, H. Saleh, K. Khalaf, M. Al-Qutayri, M. Yapici, Shakti Singh, M. Ismail
{"title":"Energy efficient system-on-chip architecture for non-invasive mobile monitoring of diabetics","authors":"M. Alhawari, A. Khandoker, B. Mohammad, H. Saleh, K. Khalaf, M. Al-Qutayri, M. Yapici, Shakti Singh, M. Ismail","doi":"10.1109/DTIS.2013.6527805","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527805","url":null,"abstract":"This paper presents an integrated biomedical processor system consists of a biomedical processor chip, MEMS-based ECG and oximetry-based Glucose alert sensors to achieve a non-invasive home diagnostic health monitoring system for diabetics. The biomedical processor integrates various computational engines such as FFT core, CAN severity algorithm classification and wireless interface. The chip targets extremely low power consumption to enable battery-powered operation for extended period of time. The sensors will provide non-invasive monitoring of ECG signals, and blood glucose levels alert at the same physical location on the human body. The unique sensor platform inevitably drives the SoC architecture to be wearable and less intrusive; thereby, providing patients with constant feedback on their critical health parameters.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115094295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
New synthesis approach of hierarchical benchmarks for hardware prototyping 硬件原型分层基准的新综合方法
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527770
M. Turki, Z. Marrakchi, M. Abid
{"title":"New synthesis approach of hierarchical benchmarks for hardware prototyping","authors":"M. Turki, Z. Marrakchi, M. Abid","doi":"10.1109/DTIS.2013.6527770","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527770","url":null,"abstract":"Hardware prototyping is becoming increasingly important in the system on chip design cycle. It allows a fast hardware verification within the time to market constraints before reaching the manufacturing phase. However, in the prototyping cycle, designs must be synthesized and mapped into logic gates. The synthesis runtime is very big and does not satisfies the hardware prototyping goals. In this paper we propose a new synthesis methodology which reduces the traditional synthesis runtime. This approach can automatically synthesize large and hierachical designs with a compromise between runtime and optimization. Experimentally, this new approach offers an improvement by an average of 60% compared to the synthesis runtime of an existing commercial tool.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121186961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Synthesis of multiple fault oriented test groups from single fault test sets 从单个故障测试集合成多个面向故障的测试组
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527786
R. Ubar, S. Kostin, J. Raik
{"title":"Synthesis of multiple fault oriented test groups from single fault test sets","authors":"R. Ubar, S. Kostin, J. Raik","doi":"10.1109/DTIS.2013.6527786","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527786","url":null,"abstract":"A novel approach for testing and diagnosing of multiple faults is discussed. A definition of a test group is introduced to cope with the problem of fault masking. The conditions are introduced to prove that a test group is sufficient to avoid fault masking. A method is presented for generating test groups regarding fault masking. Unlike the traditional test approaches, we do not target the faults as test objectives. The goal is to verify the correctness of a part of the circuit. The whole test sequence is presented as a set of test groups where each group has the goal to identify the correctness of a selected part of a circuit. The method facilitates fault diagnosis in the presence of multiple faults. Experimental research investigates the feasibility of the method and shows a way for tradeoffs between the test cost and robustness of the test regarding multiple faults.","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121041549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement 用于鲁棒性评估和改进的EPC 1类GEN 2超高频RFID标签模拟器
2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) Pub Date : 2013-03-26 DOI: 10.1109/DTIS.2013.6527771
Omar Abdelmalek, D. Hély, V. Beroulle
{"title":"EPC Class 1 GEN 2 UHF RFID tag emulator for robustness evaluation and improvement","authors":"Omar Abdelmalek, D. Hély, V. Beroulle","doi":"10.1109/DTIS.2013.6527771","DOIUrl":"https://doi.org/10.1109/DTIS.2013.6527771","url":null,"abstract":"RFID ICs such as EPC Class 1 GEN2 tag are low cost tags which are in some cases used for critical or secure applications. Increasing their robustness is not trivial due to the wide range of error sinks (EM perturbations, attacks...). Moreover increasing the robustness must have a minimum impact on the die area but also must fit with a standardized protocol. In this work we propose a design methodology in order to develop hardened digital tag architecture with a dedicated verification environment taking into account all RFID system parameters","PeriodicalId":218486,"journal":{"name":"2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117275475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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