Self-impact of NBTI effect on the degradation rate of threshold voltage in PMOS transistors

Abstract

Reliability aware circuit design and estimation of circuit performance during lifetime is a critical challenge in design and test of integrated circuits in nanometer technology nodes. Negative Bias Temperature Instability (NBTI) as the most dominant aging source is deeply dependent on the operating temperature of the circuit. In this work, we have developed a simulation framework to dynamically estimate the effect of NBTI on power consumption of the circuit and consequently the operating temperature. The effect of NBTI on temperature will act as a natural negative feedback mechanism to reduce the degradation rate of threshold voltage (Vth). Simulation results show that estimated degradation in Vth is about 4.1% less than the predicted amount by current models.