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2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)最新文献

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A class of H∞ filter design for continue-time systems with time-varying delay 一类时变时滞连续系统的H∞滤波器设计
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2010-05-26 DOI: 10.1109/CCDC.2010.5499097
Jinliang Liu, Xufang Xie, D. Yue
{"title":"A class of H∞ filter design for continue-time systems with time-varying delay","authors":"Jinliang Liu, Xufang Xie, D. Yue","doi":"10.1109/CCDC.2010.5499097","DOIUrl":"https://doi.org/10.1109/CCDC.2010.5499097","url":null,"abstract":"This paper proposes a class of H∞ filter design for continue-time systems with time-varying delay. By using the convexity property of the matrix inequality, new criteria are derived for the H∞ performance analysis of the filtering-error systems, which can lead to much less conservative analysis results and thus reduce the overdesign of the filter. Finally, a numerical example is given to demonstrate the effectiveness and the merit of the proposed method.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130168797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power misprediction recovery mechanism 低功耗错误预测恢复机制
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-12-01 DOI: 10.1109/PRIMEASIA.2009.5397409
Jiongyao Ye, Takahiro Watanabe
{"title":"A low-power misprediction recovery mechanism","authors":"Jiongyao Ye, Takahiro Watanabe","doi":"10.1109/PRIMEASIA.2009.5397409","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397409","url":null,"abstract":"In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance. Previous researches proposed dual (or multi) path execution methods attempt to reduce the misprediction penalty, but these methods are quite complex and high power consumption. Most of the reasons are due to simultaneously fetching and executing instructions from multiple. In this paper, we reduce branch misprediction penalties based on the balance between complexity, power, and performance. We present a novel technique-Decode Recovery Cache (DRC) - for reducing misprediction penalty, giving consideration to complexity and power consumption simultaneously. The DRC stores decoded instructions that are mispredicted. Then during subsequent mispredictions, a hit in the DRC can reduce the re-fill time of pipeline, and eliminate instruction re-fetch and its subsequent decoding. The bypassing of both re-fetching and re-decoding reduces processor power. Experimental results employing SPECint 2000 benchmark show that, using a processor with DRC, IPC value is significantly improved by 10.4% on average over the traditional processors and average power consumption is reduced by 62.6%, compared with dual Path Instruction Processing.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122891329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 88dB 48 KHz full feed-forward sigma-delta modulator 88dB 48khz全前馈σ - δ调制器
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397380
Congyi Zhu, Yaohui Zhang, Wenlong Ma, Hailin XiaoP, Hongbing Liu, Jing He
{"title":"An 88dB 48 KHz full feed-forward sigma-delta modulator","authors":"Congyi Zhu, Yaohui Zhang, Wenlong Ma, Hailin XiaoP, Hongbing Liu, Jing He","doi":"10.1109/PRIMEASIA.2009.5397380","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397380","url":null,"abstract":"This paper examines the design of full feed-forward sigma-delta modulator which is much more suitable for the CMOS digital process with low supply voltage than the traditional second-order feedback loop. The full feed-forward system reduces the modulator's sensitivity of the circuit nonidealities and decreases the internal signal swing to half the full scale. An implementation in a 0.35um CMOS technology achieved dynamic range of 88dB, bandwidth of 48 KHz and power consumption of 5mW. It can operate from supply voltages ranging from 2.4v–3.3v. The architecture is quite useful for low voltage SOC applications, such as portable biomedical system. (Abstract)","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel method of straight-line extraction based on wallis filtering for the close-range building 一种基于墙体滤波的近景建筑物直线提取新方法
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397390
Chang Li, Hongmin Wu, Min Hu, Yongqiang Zhou
{"title":"A novel method of straight-line extraction based on wallis filtering for the close-range building","authors":"Chang Li, Hongmin Wu, Min Hu, Yongqiang Zhou","doi":"10.1109/PRIMEASIA.2009.5397390","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397390","url":null,"abstract":"3D reconstruction based on high-level features, such as line and plane, is an important development trend in Digital Photogrammetry and Computer Vision. A novel method for extracting stratight line is presented, which can be illustrated as follows. Firstly, image is preprocessed by Wallis filtering that is used to enhance the image contrast and reduce the noise, so it is easy to extract more lines. Secondly, Laplacian of Gaussian operator (LOG) algorithm is implemented to locate the edge by detecting discontinuity variation in image. Thirdly, feature grouping (perceptual organization) and line fitting with hypothesis testing are utilized for combining and fitting fractured short line segments into a whole line, which not only can overcome the deficiency of Hough transform but also can avoid misconnecting grouped collinear lines. Lastly, the least square template matching algorithm (LSTM) is done to get higher precise located lines. The experimental results show that the proposed algorithm by us is more efficient and reliable, which can get richer and higher accurate (sub-pixel) straight line information, especially for the close-range image of building.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127502356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Research and design of level converter circuit for I/O ports I/O口电平转换电路的研究与设计
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397343
Yi-zhong Yang, Guang-jun Xie, Xuan Zhao
{"title":"Research and design of level converter circuit for I/O ports","authors":"Yi-zhong Yang, Guang-jun Xie, Xuan Zhao","doi":"10.1109/PRIMEASIA.2009.5397343","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397343","url":null,"abstract":"A level converter circuit for I/O ports from 3.3V LVTTL logic to 1.8V CMOS logic with TSMC 0.18um CMOS process has been designed. Level converter circuit has been integrated in an Integrated Circuit, which use single supply voltage. A positive feedback circuit similar to the Schmitt Flip-Flop is adopted to realize the level conversion, which also acts as both a buffer and a waveform shaping role. ESD protection circuit is implemented by the diode and resistor circuit structure traditionally. Signal acquisition circuit use a D flip-flop consisted of the structure of CMOS transmission gate. A number of suitable buffers are used to link up them. The circuit has been used in an IC, which works on 250MHz. The result shows that design satisfies design requirement exactly.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125577117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cooperative schemes for two-way relaying protocol 双向中继协议的合作方案
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397449
Chunguo Li, Luxi Yang, Weiping Zhu, Zhenya He
{"title":"Cooperative schemes for two-way relaying protocol","authors":"Chunguo Li, Luxi Yang, Weiping Zhu, Zhenya He","doi":"10.1109/PRIMEASIA.2009.5397449","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397449","url":null,"abstract":"In this paper, three cooperative relaying schemes are proposed for relay networks comprised of two source terminals and multiple relays, each with single antenna. The new relaying schemes, corresponding to the maximum ratio combining of the downlink and uplink channels, phase rotation of the received signals at relays, and the channel gain equalization, are designed based on the maximization of the sum rate of the relay network subject to a total relay power constraint. Numerical simulations are conducted to illustrate the performance of the proposed schemes in terms of the capacity and the cumulative distribution function of the cooperative network.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115107148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
IIGA based algorithm for cooperative jamming resource allocation 基于IIGA的协同干扰资源分配算法
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397370
Xiaoke Zhai, Zhuang Yi
{"title":"IIGA based algorithm for cooperative jamming resource allocation","authors":"Xiaoke Zhai, Zhuang Yi","doi":"10.1109/PRIMEASIA.2009.5397370","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397370","url":null,"abstract":"This paper addresses a cooperative jamming resource allocation problem in electronic warfare and presents a resource allocation model of cooperative jamming (CJRA). Besides the capabilities and number of available jamming resources, the model also takes many constrains into account. Then an improved immune genetic algorithm (IIGA) is presented to solve the problem. In order to prevent the algorithm from converging too slowly like traditional immune genetic algorithm, IIGA introduces the mechanisms of immunological memory and immunological metabolism which can restrain the individuals from degenerating in the process of evolution. In the end, the simulation indicates that the algorithm can resolve the problem of CJRA effectively and shorten the time of decision-making.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116530733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An efficient and robust zero-watermarking scheme for audio based on DWT and DCT 基于DWT和DCT的高效鲁棒音频零水印方案
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397403
Hua-liang Dai, Di He
{"title":"An efficient and robust zero-watermarking scheme for audio based on DWT and DCT","authors":"Hua-liang Dai, Di He","doi":"10.1109/PRIMEASIA.2009.5397403","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397403","url":null,"abstract":"A zero-watermarking scheme for audio based on the steady sign of certain DWT-DCT coefficients with maximal absolute value, is proposed. Compared with traditional watermarking schemes, the proposed scheme can solve the contradiction between robustness and imperceptibility perfectly without introducing audio quality degradation as occurred usually in traditional watermarking schemes. The multiresolution characteristic of discrete wavelet transform (DWT), the energy compression characteristic of discrete cosine transform (DCT) and the steady sign of certain DWT-DCT coefficients are combined to extract important features from the host audio signal, which are used to construct the secret key with the watermark image. Simulation results show that the proposed scheme has stronger robustness as well as security, as compared to the schemes in [5] and [8].","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122378372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 10ppm/°C 1.8V piecewise curvature-corrected bandgap reference in 0.5µm CMOS 一个10ppm/°C 1.8V分段曲率校正带隙参考在0.5µm CMOS
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397355
Jinghu Li, Xing-bao Zhang, Ming-yan Yu, Liang Han
{"title":"A 10ppm/°C 1.8V piecewise curvature-corrected bandgap reference in 0.5µm CMOS","authors":"Jinghu Li, Xing-bao Zhang, Ming-yan Yu, Liang Han","doi":"10.1109/PRIMEASIA.2009.5397355","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397355","url":null,"abstract":"A piecewise curvature-corrected bandgap reference (BGR) is presented. It features in utilizing a piecewise curvature-corrected current generator and an operational amplifier biased by a current proportional to absolute temperature (PTAT) to a conventional first order BGR. The piecewise current corrects the nonlinear temperature term of the first-order BGR in the higher temperature range (TR). The PTAT biased current compensates the trans-conductance degradation of the operational amplifier with temperature. Measured result shows that the proposed BGR achieves temperature coefficient of 10ppm/°C in the TR of 10–125°C, line regulation of 1.8mV/V in the supply range of 1.7–4.0V, power supply rejection(PSR) of −48dB. It is fabricated in CSMC0.5µm mixed signal CMOS process with chip area of 400×300µm and power consumption of 48µW.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128725839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Zero skew clock synthesis in VLSI design VLSI设计中的零倾斜时钟合成
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397410
Guirong Wu, S. Jia, Y. Wang, Ganggang Zhang
{"title":"Zero skew clock synthesis in VLSI design","authors":"Guirong Wu, S. Jia, Y. Wang, Ganggang Zhang","doi":"10.1109/PRIMEASIA.2009.5397410","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397410","url":null,"abstract":"This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into smaller partitions, and the clock buffers are inserted as pseudo clock sources to drive each portion. The automatic place and route (APR) tool may synthesize each clock subtree with better performance. The proposed methodology is applied to a chip level clock tree network and achieves good results.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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