一个10ppm/°C 1.8V分段曲率校正带隙参考在0.5µm CMOS

2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI:10.1109/PRIMEASIA.2009.5397355

Jinghu Li, Xing-bao Zhang, Ming-yan Yu, Liang Han

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引用次数: 7

摘要

提出了一种分段曲率校正带隙基准(BGR)。它的特点是利用分段曲率校正电流发生器和一个运算放大器，其偏置电流与绝对温度(PTAT)成比例，与传统的一阶BGR相匹配。分段电流在较高温度范围内修正了一阶BGR的非线性温度项。PTAT偏置电流补偿运算放大器随温度的跨导退化。实测结果表明，所提出的BGR在TR为10 ~ 125℃时温度系数为10ppm/℃，在供电范围为1.7 ~ 4.0V时线路稳压为1.8mV/V，电源抑制(PSR)为−48dB。采用CSMC0.5µm混合信号CMOS工艺制作，芯片面积400×300µm，功耗48µW。

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A 10ppm/°C 1.8V piecewise curvature-corrected bandgap reference in 0.5µm CMOS

A piecewise curvature-corrected bandgap reference (BGR) is presented. It features in utilizing a piecewise curvature-corrected current generator and an operational amplifier biased by a current proportional to absolute temperature (PTAT) to a conventional first order BGR. The piecewise current corrects the nonlinear temperature term of the first-order BGR in the higher temperature range (TR). The PTAT biased current compensates the trans-conductance degradation of the operational amplifier with temperature. Measured result shows that the proposed BGR achieves temperature coefficient of 10ppm/°C in the TR of 10–125°C, line regulation of 1.8mV/V in the supply range of 1.7–4.0V, power supply rejection(PSR) of −48dB. It is fabricated in CSMC0.5µm mixed signal CMOS process with chip area of 400×300µm and power consumption of 48µW.

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2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

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