Zero skew clock synthesis in VLSI design

Abstract

This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into smaller partitions, and the clock buffers are inserted as pseudo clock sources to drive each portion. The automatic place and route (APR) tool may synthesize each clock subtree with better performance. The proposed methodology is applied to a chip level clock tree network and achieves good results.