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Pattern bandwidth improving of printed notched-monopole antenna 提高印刷缺口单极天线的方向图带宽
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397438
Weiwen Li, Li-Peng Cai, B. You, Changbin Huang
{"title":"Pattern bandwidth improving of printed notched-monopole antenna","authors":"Weiwen Li, Li-Peng Cai, B. You, Changbin Huang","doi":"10.1109/PRIMEASIA.2009.5397438","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397438","url":null,"abstract":"A printed monopole antenna of the tapered and notched radiator with the microstrip feed-line is designed. The simulated and measured results show that the printed antenna achieves a broad impedance bandwidth of 3.1–11.1 GHz for the 10-dB return loss. This antenna features the stable omni-directional radiation patterns over the impedance bandwidth. Using the current distribution modes the influence of the radiator cut on the radiation performance is analyzed. It is indicated that the notched radiator can improve the pattern bandwidth due to the enhanced standing-wave current by the cut at the high frequency. Compared with the cut depth, the cut width performs more important functions on the radiation characteristics. To maintain the similar radiating performance, the width of the residual lower-side patch of the notched radiator must be larger than one eighth of the high-frequency resonant wavelength.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power reconfigurable mixer for MB-OFDM UWB receivers 用于MB-OFDM UWB接收机的低功耗可重构混频器
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397437
Yang Gao, F. Huang, Lianhong Wu, Jia Hua Cheng
{"title":"A low-power reconfigurable mixer for MB-OFDM UWB receivers","authors":"Yang Gao, F. Huang, Lianhong Wu, Jia Hua Cheng","doi":"10.1109/PRIMEASIA.2009.5397437","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397437","url":null,"abstract":"This paper presents a low-power down-conversion mixer for 3.1∼4.8 GHz MB-OFDM UWB applications. The proposed mixer is based on folded double-balanced Gilbert cell and employs following techniques: two cross-coupling capacitors at the transconductance stage enhance conversion gain and reduce input noise; two choke inductors reduce flicker noise from the switch quad; tuning capacitors and resistors are added to fit different UWB bands. Designed in SMIC 0.13 µm CMOS process, post-simulation results show a conversion gain of 8.2 to 9.7 dB, a single-sideband noise figure of 10.4 to 12.4 dB, and an input third-order intercept point of −3.2 to −1.2 dBm over 3.1∼4.8 GHz band. The mixer core dissipates 3.7 mW under 1.2 V supply, and the total area of the layout is 0.81×0.5 mm2. Based on the proposed topology, an overall 3.1∼10.6 GHz MB-OFDM UWB mixer can be designed with barely any more power consumption and circuit complexity.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Mean shift tracking with Kernel Co-Occurrence Matrices 基于核共现矩阵的均值移位跟踪
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397400
Jianjun Chen, Suofei Zhang, Zhen-yang Wu, Guocheng An
{"title":"Mean shift tracking with Kernel Co-Occurrence Matrices","authors":"Jianjun Chen, Suofei Zhang, Zhen-yang Wu, Guocheng An","doi":"10.1109/PRIMEASIA.2009.5397400","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397400","url":null,"abstract":"We construct Kernel Co-occurrence Matrices (KCMs) to represent the target model and the target candidates. Then those matrices are employed as the tracking cues in mean shift framework. Some improvements are presented in the implementation of the algorithm. First, the angle relation between pixel-pairs is redefined to depict the asymmetric characteristic of the object. Second, the KCMs of the target model and the candidates are normalized to a same integer to increase calculation accuracy. Third, the computation of each pixel weight is modified to improve operation speed. The tracking results of several real world sequences with dark illumination or lighting variance show that the proposed algorithm can track the target effectively.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124453738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Configurable secure ECC hardware module for resource constrained device 可配置安全ECC硬件模块，用于资源受限的设备
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397353
Qian Xu, Yujie Zhou, Junfa Mao
{"title":"Configurable secure ECC hardware module for resource constrained device","authors":"Qian Xu, Yujie Zhou, Junfa Mao","doi":"10.1109/PRIMEASIA.2009.5397353","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397353","url":null,"abstract":"in this paper, a novel ECC hardware module that provides different secure levels for resource constrained device is introduced. We adopt MOF left-to-right recoding scheme to achieve small area. Moreover, the design reduces the area cost of modular inversion by exploring reusability. Another distinct feature associated with this module is that an MOF based SPA-resistant algorithm is proposed to offer configurable protections against SPA. This algorithm not only reduces dummy operations, but also has a low additional cost. Finally, the ECC core is evaluated under SMIC 0.18-µm technology. Our design using totally 87K gates achieves operation times of 2.46 ms without countermeasures and 3.53 ms with countermeasures for 160-bit scalar multiplication in GF (p) at 100 MHz.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121599304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Contrast research on interpolation and subpixel imaging in CCD geometric superresolution reconstruction CCD几何超分辨重建中插值与亚像素成像的对比研究
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397387
W. Ge, Yong-sen Xu, L. Zhai, Zhengping Xu, Shou-wang Yang
{"title":"Contrast research on interpolation and subpixel imaging in CCD geometric superresolution reconstruction","authors":"W. Ge, Yong-sen Xu, L. Zhai, Zhengping Xu, Shou-wang Yang","doi":"10.1109/PRIMEASIA.2009.5397387","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397387","url":null,"abstract":"In order to enhance the resolution of Charge Coupled Device(CCD)pixel with the pixel dimension and focal length of optical system unchanged, the problem of CCD geometric superresolution is educed. The problem is discussed in terms of software and hardware. In software, the bicubic interpolation is introduced, while in hardware, the subpixel imaging method is utilized. The subpixel imaging method integrates two uniform linear CCDs staggered by half dimension of pixel in one device. In operation, the line frequency is doubled. At last, the collected data is interweaved to synthesize a high resolution image. The two methods, bicubic interpolation and subpixel imaging, are simulated with Matlab7.0.1. The qualitative and quantitative analyses are given. The simulated results of lanczos and cubic spline interpolation methods are given simultaneously to show the performance of interpolation. The simulation result shows that the result images quality becomes better in both methods, but compared with bicubic interpolation method, the synthesized image PSNR gained from sub-pixel imaging is averagely enhanced by 2.1682dB, while the elapsed time is reduced to be about one forth. The subpixel imaging method could significantly mitigate the image blur introduced by under-sample.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132527489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A method of error correction for digital class D power amplifier 数字D类功率放大器的误差校正方法
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397423
Zeqi Yu, Huiqiong Feng
{"title":"A method of error correction for digital class D power amplifier","authors":"Zeqi Yu, Huiqiong Feng","doi":"10.1109/PRIMEASIA.2009.5397423","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397423","url":null,"abstract":"Because of the nonlinearity of digital PWM generator and the effect of power supply noise in power stage, the error is introduced into digital class D power amplifier. A method used to eliminate the error is presented in this paper, and it is easy to implement. Based on this method, a digital class D power amplifier is designed and simulated, the simulation results indicate this method can basically eliminate the error produced by digital PWM generator and power stage, and improve the performance of the system.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134282755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1-volt, 2.5-mW, 2.4-GHz frequency synthesizer in 0.35-µm CMOS technology 1伏，2.5 mw, 2.4 ghz频率合成器，采用0.35µm CMOS技术
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397460
Jun‐Kai Tan, Y. Lian
{"title":"A 1-volt, 2.5-mW, 2.4-GHz frequency synthesizer in 0.35-µm CMOS technology","authors":"Jun‐Kai Tan, Y. Lian","doi":"10.1109/PRIMEASIA.2009.5397460","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397460","url":null,"abstract":"In this paper, we present a low voltage, low power, 2.4-GHz frequency synthesizer designed in 0.35-µm CMOS technology. The frequency synthesizer is implemented with an Integer-N phase-locked loop (PLL). The PLL can achieve a frequency tuning step of 1-MHz and is capable of covering the whole 2.4-GHz ISM band. The voltage controlled oscillator (VCO) output frequency is firstly divided by a novel tri-modulus current-mode prescaler. The prescaler output is converted to rail-to-rail swing and drives the true single phase clocked register (TSPC) CMOS counters. The loop filter is designed to be 2nd order and implemented off-chip with passive devices. The post-layout simulation results show that the phase noise of the VCO is −107 dBc/Hz at 1 MHz offset, and the PLL reference spur level of the PLL is below −50 dBc.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133547863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of three important peripheral circuits of SRAM based on 9T cell 基于9T单元的SRAM三个重要外围电路的设计
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397378
H. Zhao, Bingshi Xu
{"title":"Design of three important peripheral circuits of SRAM based on 9T cell","authors":"H. Zhao, Bingshi Xu","doi":"10.1109/PRIMEASIA.2009.5397378","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397378","url":null,"abstract":"Read stability issue is becoming more and more concerned in accordance with rapid development of CMOS IC fabrication technology. A new nine transistor (9T) SRAM cell with enhanced stability during a read operation and reduced power consumption is proposed recently. To put it into practical an SRAM based on it needs to be built. This paper designs three peripheral circuits that are needed in the building process, including row-selecting circuit suitable for the dual control signal character of 9T SRAM cell, simplified writing circuit that can effectively pull down the bit-lines and choose which to pull with only three N-type transistors and power-reduced sense amplifier with its switch transistor controlled by the logic ‘and’ result of one external and two internal signals that can shut down the circuit when there is enough voltage difference between outputs. The active power consumption of the sense amplifier with and-gate is 38% lower than the one without it. An 8-kb SRAM based on 9T cell using peripheral circuits proposed in this paper is built, and the correctness of the simulation result of its functionality shows that SRAM based on 9T cell can work well with proposed peripheral circuits.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115190243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a configurable fixed-point multiplier for digital signal processor 数字信号处理器可配置定点乘法器的设计
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397407
Xinyue Zhang, Zhaolin Li, Qingwei Zheng
{"title":"Design of a configurable fixed-point multiplier for digital signal processor","authors":"Xinyue Zhang, Zhaolin Li, Qingwei Zheng","doi":"10.1109/PRIMEASIA.2009.5397407","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397407","url":null,"abstract":"A configurable fixed-point multiplier for digital signal processing (DSP) applications is proposed in this paper. It is implemented in four pipeline stages. The proposed multiplier supports multiple-precision operations, including one 32×32, two 16×32, two 16×16 or four 8×8 signed/unsigned multiplication operations and 16-bit or 8-bit dot product/double dot product operations. It is modeled in VerilogHDL and synthesized in 0.13 µm CMOS technology. The critical path delay of the proposed design is 1.69 ns.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114313687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optimization of Power/Ground network considering area, performance and power consumption 考虑面积、性能和功耗的电源/接地网络优化
2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) Pub Date : 2009-11-01 DOI: 10.1109/PRIMEASIA.2009.5397350
Yuehui Shi, Donghua Wu, Zhiguo Bao, Takahiro Watanabe
{"title":"Optimization of Power/Ground network considering area, performance and power consumption","authors":"Yuehui Shi, Donghua Wu, Zhiguo Bao, Takahiro Watanabe","doi":"10.1109/PRIMEASIA.2009.5397350","DOIUrl":"https://doi.org/10.1109/PRIMEASIA.2009.5397350","url":null,"abstract":"Due to the importance of Power/Ground network, lots of researches have been made on it. But they only focused on the minimal area of it. By discussion on the relation among Vdd, performance and power consumption, this paper proposes an optimal algorithm using GA and SLP method where area, performance and power consumption can be simultaneously evaluated. As a result, the Power/Ground network is designed by adjusting the wire width to supply the proper Vdds. The convergence of the algorithm is proved. Experimental results and simulations also show that the proposed algorithm can produce a good Power/Ground network.","PeriodicalId":217369,"journal":{"name":"2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114766823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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