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Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium最新文献

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A research study to establish the need to implement cycle time reduction strategies for new package introduction 一项研究，以确定需要实施周期时间减少战略的新包装引进
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398187
M. Goetsch
{"title":"A research study to establish the need to implement cycle time reduction strategies for new package introduction","authors":"M. Goetsch","doi":"10.1109/IEMT.1993.398187","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398187","url":null,"abstract":"The research is an ex-post facto design administered to a randomly sampled population of the assembly technology groups within one large semiconductor company. The results confirm the fact that cycle time reduction strategies need to be managed more effectively. The areas determined to be of greatest need and importance are organizational structure and development methodology. Recommended strategies include removal of barriers between functional groups, rigorous application of team building sessions, regular project updates, priority reviews for design, development, and manufacturing personnel, and delegating routine decisions to lower-level personnel. Training programs for manufacturing personnel should be made a high priority in the development phase, and rigorous requirements for technology transfer, including detailed documentation, are necessary to guarantee successful implementation of the new technology.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130327690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Neural network-based modeling of the plasma-enhanced chemical vapor deposition of silicon dioxide 基于神经网络的等离子体增强化学气相沉积二氧化硅的建模
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398164
Seung-Soo Han, M. Ceiler, S. A. Bidstrup, Paul A. Kohl, Gary S. May
{"title":"Neural network-based modeling of the plasma-enhanced chemical vapor deposition of silicon dioxide","authors":"Seung-Soo Han, M. Ceiler, S. A. Bidstrup, Paul A. Kohl, Gary S. May","doi":"10.1109/IEMT.1993.398164","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398164","url":null,"abstract":"The properties of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide films are modeled using neural networks. This method is simple, extremely useful and readily applicable to the empirical modeling of such complex plasma processes. In characterizing the SiO/sub 2/ films, it is found that the dominant film property is its impurity concentration. The impurity concentration dictates the refractive index and permittivity, two critical figures of merit when these films are used as interlayer dielectric and in optoelectronic applications. The most important parameters in determining the impurity concentration of the films are substrate temperature and pressure. Increasing the substrate temperature causes the impurity concentration to decrease. This drop in impurity concentration causes an increase in refractive index and a decrease in permittivity. Increasing pressure has almost the same effect, causing a decrease in permittivity.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130916199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reactive scheduling of a semiconductor testing facility 半导体测试设备的反应调度
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398156
C. N. Perry, R. Uzsoy
{"title":"Reactive scheduling of a semiconductor testing facility","authors":"C. N. Perry, R. Uzsoy","doi":"10.1109/IEMT.1993.398156","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398156","url":null,"abstract":"The authors describe an approach to scheduling complex job shops such as semiconductor testing operations which uses the global shop-floor information available from computerized Factory Control Systems. The approach combines a decomposition approach for the static problem with an EDR approach to handling the dynamic events in the system. Preliminary experiments show that these rescheduling policies have performance comparable to myopic dispatching rules, and the implementation of better subproblem solution methods in the decomposition should lead to substantial further improvements.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Neural network control of a plasma gate etch: Early steps in wafer-to-wafer process control 等离子栅蚀刻的神经网络控制:晶圆到晶圆过程控制的早期步骤
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398165
E. Rietman, S. Patel, E. Lory
{"title":"Neural network control of a plasma gate etch: Early steps in wafer-to-wafer process control","authors":"E. Rietman, S. Patel, E. Lory","doi":"10.1109/IEMT.1993.398165","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398165","url":null,"abstract":"A gate oxide thickness controller for a plasma etch reactor has been developed. This controller is for 0.9-/spl mu/m technology. By monitoring certain processes, signatures are fed forward into a neural network trained by the backpropagation method. It is possible to predict in real time the correct over-etch time on a wafer-by-wafer basis. Computer simulations indicate that the neural network is equivalent to humans for this task. The uniqueness of this controller is compared with a previous controller for a 1.25-/spl mu/m technology gate etch process.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115818977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Impact of low-cost MCM-D on MCM designers' technology choices 低成本MCM- d对MCM设计者技术选择的影响
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398160
C. Ho, H. Green
{"title":"Impact of low-cost MCM-D on MCM designers' technology choices","authors":"C. Ho, H. Green","doi":"10.1109/IEMT.1993.398160","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398160","url":null,"abstract":"Multichip module (MCM)-D has been portrayed as the technology with the most promise, the greatest ability to handle high clock frequencies, and the long-term choice for high-performance applications - although always with a warning that MCM-D was many times more expensive a technology choice than MCM-L. These assumptions are rapidly becoming invalid. MCM-D performance has emerged as foreseen, but at the same time prices for completed modules have fallen greatly. Economics of scale have allowed MCM-D manufacturers to take advantage of their technology by building products that only MCM-D line geometries and form factors make possible. In addition, any enabling technology - like 3-D memory or 3-D stacking of MCM's - for MCM-L will also be usable to equal or greater effect by MCM-D. MCM applications are continuing to follow long-term industry trends for higher performance, lower costs, and smaller form factors.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114722314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integrated BiCMOS process and circuit development using SPR 基于SPR的集成BiCMOS工艺及电路开发
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398216
R. Ryter, R. Zingg, C. Hegarty, W. Fichtner, E. Doering
{"title":"Integrated BiCMOS process and circuit development using SPR","authors":"R. Ryter, R. Zingg, C. Hegarty, W. Fichtner, E. Doering","doi":"10.1109/IEMT.1993.398216","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398216","url":null,"abstract":"An integrated process development environment is described. Geometry information for process simulation is taken automatically from a commercial layout tool, and process step information exists in a high-level language databank. Doping information can be read by a device simulator, permitting SPICE (simulation program with IC emphasis)-like circuit simulation. This environment is presented in a BiCMOS development context.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128595381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Pattern defect analysis and evaluation of printed circuit boards using CAD data 基于CAD数据的印刷电路板图案缺陷分析与评价
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398230
M. Ito, I. Fujita, Y. Takeuchi, Tooru Uchida
{"title":"Pattern defect analysis and evaluation of printed circuit boards using CAD data","authors":"M. Ito, I. Fujita, Y. Takeuchi, Tooru Uchida","doi":"10.1109/IEMT.1993.398230","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398230","url":null,"abstract":"A methodology for optical inspection of large printed circuit boards using their original artwork data or CAD data is presented. The manufacturing process and some ambient and control conditions are evaluated directly from the optical image using the absolute data. An accurate automatic inspection system can be also expected. The experimental evaluation shows that an optimal size of the allowable skeletons margin is about 40 to 50% of the average width of the conductor patterns. The inspecting skeletons should be sampled at variable intervals, rather than taking all the pixels of the skeletons, so that the accuracy and the comparison time may be compromised. These preliminary experiments are essential for the practical development of the system. It is demonstrated how the current system is improved from conventional ones in many aspects.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128890056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An automated low-solids flux concentration analyzer 自动低固体通量浓度分析仪
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398209
P. Brownell, D.D. Lindig
{"title":"An automated low-solids flux concentration analyzer","authors":"P. Brownell, D.D. Lindig","doi":"10.1109/IEMT.1993.398209","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398209","url":null,"abstract":"A flux concentration analyzer system based on an ultraviolet photometer is described. It is used successfully online in a foam fluxer during assembly of printed circuit boards. The system provides solvent regulation for low-solids fluxes with greater precision than control mechanisms based on measurements of the specific gravity ratio.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126541025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated visual inspection for IC wire-bond using auto-focusing technique 采用自动对焦技术的集成电路线键自动目视检测
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398225
H. Lim, Wei Zhang, L. M. Koh
{"title":"Automated visual inspection for IC wire-bond using auto-focusing technique","authors":"H. Lim, Wei Zhang, L. M. Koh","doi":"10.1109/IEMT.1993.398225","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398225","url":null,"abstract":"An automated integrated circuit (IC) wire-bond inspection system has been successfully developed. The system is capable of measuring the height and diameter of the bonds. The bond height is detected by automatically computing the focused planes of the top and the base of the bond with a series of two-dimensional images of the bond. The focused plane of an image is obtained by extracting the high-frequency features of the image. By scanning horizontally and vertically for a steep change in gray level of the image, the diameter of the bond is calculated. The system carries out the measurement task at a speed of six bonds per minute. Precision of /spl plusmn/0.9 /spl mu/m and /spl plusmn/2.0 /spl mu/m for the height and diameter measurement can be obtained.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128199077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Microstructural evolution and mechanical properties of Sn-Bi based solders 锡铋基钎料的显微组织演变及力学性能
Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium Pub Date : 1993-10-04 DOI: 10.1109/IEMT.1993.398212
C. Raeder, L. Felton, D. Knorr, G.B. Schmeelk, D. Lee
{"title":"Microstructural evolution and mechanical properties of Sn-Bi based solders","authors":"C. Raeder, L. Felton, D. Knorr, G.B. Schmeelk, D. Lee","doi":"10.1109/IEMT.1993.398212","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398212","url":null,"abstract":"An overview of issues relevant to reliability of Sn-Bi solder joints is presented. The effects of aging on the microstructure of Sn-Bi solder joints are described. The results show that during aging, Sn is depleted from the solder/base metal interface. The two-phase Sn-Bi microstructure coarsens appreciably during aging. The rate of coarsening can be slowed by adding 1.0 wt% Cu to the solder. Aging also affects the mechanical properties of the solder joints in shear, where aged joints shown an increase in flow stress and plastic strain at failure. The creep properties of cast and aged Sn-Bi eutectic alloy at stresses between 0.5 and 65 MPa and temperatures between 30/spl deg/C and 120/spl deg/C are described. In the power law creep regime, cast Sn-Bi eutectic has a stress exponent of three and an activation energy of 0.6 eV.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127563337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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