2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors最新文献_第3页

Accelerating a Virtual Ecology Model with FPGAs 用fpga加速虚拟生态模型

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.27

J. Lamoureux, T. Field, W. Luk

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引用次数: 1

A 16-context Optically Reconfigurable Gate Array 一个16上下文光可重构门阵列

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.41

M. Nakajima, Minoru Watanabe

引用次数: 7

Reconfigurable SWP Operator for Multimedia Processing 用于多媒体处理的可重构SWP操作符

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.13

Shafqat Khan, E. Casseau, D. Ménard

引用次数: 9

Parallelized Architecture of Multiple Classifiers for Face Detection 多分类器在人脸检测中的并行化结构

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.38

Junguk Cho, Bridget Benson, Shahnam Mirzaei, R. Kastner

引用次数: 51

Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture 并行FFT算法在SmartCell粗粒度可重构架构上的映射

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.33

C. Liang, Xinming Huang

引用次数: 31

A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification 基于fpga的可扩展高速分组分类并行体系结构

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.17

Weirong Jiang, V. Prasanna

{"title":"A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification","authors":"Weirong Jiang, V. Prasanna","doi":"10.1109/ASAP.2009.17","DOIUrl":"https://doi.org/10.1109/ASAP.2009.17","url":null,"abstract":"Multi-field packet classification is a critical function that enables network routers to support a variety of applications such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Explosive growth of Internet traffic requires the future packet classifiers be implemented in hardware. However, most of the existing packet classification algorithms need large amount of memory, which inhibits efficient hardware implementations. This paper exploits the modern FPGA technology and presents a partitioning-based parallel architecture for scalable and high-speed packet classification. We propose a coarse-grained independent sets algorithm and then combine it seamlessly with the cross-producting scheme. After partitioning the original rule set into several coarse-grained independent sets and applying the cross-producting scheme for the remaining rules, the memory requirement is dramatically reduced. Our FPGA implementation results show that our architecture can store 10K real-life rules in a single state-of-the-art FPGA while consuming a small amount of on-chip resources. Post place and route results show that the design sustains 90 Gbps throughput for minimum size (40 bytes) packets, which is more than twice the current backbone network link rate.","PeriodicalId":202421,"journal":{"name":"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132380024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Integral Parallel Architecture & Berkeley's Motifs 整体并行建筑与伯克利的主题

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.40

M. Malita, G. Stefan

引用次数: 8

Application Specific Transistor Sizing for Low Power Full Adders 低功率全加法器专用晶体管尺寸

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.23

F. Eslami, A. Baniasadi, Mostafa Farahani

引用次数: 1

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling 具有预标度的基数-4复除法单元的设计与实现

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.32

Pouya Dormiani, M. Ercegovac, J. Muller

引用次数: 14

P3FSM: Portable Predictive Pattern Matching Finite State Machine P3FSM:便携式预测模式匹配有限状态机

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.16

L. Vespa, Minimol Mathew, N. Weng

引用次数: 11