整体并行建筑与伯克利的主题

M. Malita, G. Stefan
{"title":"整体并行建筑与伯克利的主题","authors":"M. Malita, G. Stefan","doi":"10.1109/ASAP.2009.40","DOIUrl":null,"url":null,"abstract":"The Integral Parallel Architecture (IPA) developed and actually implemented by BrightScale is a low-power(133 GOPS/Watt) & low-area (8 GOPS/mm^2) one-chip solution to solve intense computational problems using data-parallel, time-parallel and speculative-parallel mechanisms. BrightScale technology is presented from the point of view of each of the 13 motifs proposed in The Berkeley's View. IPA emerges from Kleene's computational model of the partial recursive functions as the simplest parallel architecture, a good starting point for a true science of parallel computation. We briefly investigate how such an elementary parallel architecture performs, for the main computational motifs, in solving the problems of programmability, portability, flexibility, data movement between computational cells, and between cells and the main memory.","PeriodicalId":202421,"journal":{"name":"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Integral Parallel Architecture & Berkeley's Motifs\",\"authors\":\"M. Malita, G. Stefan\",\"doi\":\"10.1109/ASAP.2009.40\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Integral Parallel Architecture (IPA) developed and actually implemented by BrightScale is a low-power(133 GOPS/Watt) & low-area (8 GOPS/mm^2) one-chip solution to solve intense computational problems using data-parallel, time-parallel and speculative-parallel mechanisms. BrightScale technology is presented from the point of view of each of the 13 motifs proposed in The Berkeley's View. IPA emerges from Kleene's computational model of the partial recursive functions as the simplest parallel architecture, a good starting point for a true science of parallel computation. We briefly investigate how such an elementary parallel architecture performs, for the main computational motifs, in solving the problems of programmability, portability, flexibility, data movement between computational cells, and between cells and the main memory.\",\"PeriodicalId\":202421,\"journal\":{\"name\":\"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASAP.2009.40\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.2009.40","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

由BrightScale开发并实际实施的集成并行架构(IPA)是一种低功耗(133 GOPS/Watt)和低面积(8 GOPS/mm^2)的单芯片解决方案,可使用数据并行、时间并行和推测并行机制解决密集的计算问题。BrightScale技术是从《伯克利的观点》中提出的13个主题中的每一个的角度来呈现的。IPA从Kleene的部分递归函数的计算模型中脱颖而出,作为最简单的并行架构,这是真正的并行计算科学的一个很好的起点。我们简要地研究了这样一个基本的并行架构是如何执行的,对于主要的计算主题,在解决可编程性、可移植性、灵活性、计算单元之间以及单元与主存储器之间的数据移动等问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Integral Parallel Architecture & Berkeley's Motifs
The Integral Parallel Architecture (IPA) developed and actually implemented by BrightScale is a low-power(133 GOPS/Watt) & low-area (8 GOPS/mm^2) one-chip solution to solve intense computational problems using data-parallel, time-parallel and speculative-parallel mechanisms. BrightScale technology is presented from the point of view of each of the 13 motifs proposed in The Berkeley's View. IPA emerges from Kleene's computational model of the partial recursive functions as the simplest parallel architecture, a good starting point for a true science of parallel computation. We briefly investigate how such an elementary parallel architecture performs, for the main computational motifs, in solving the problems of programmability, portability, flexibility, data movement between computational cells, and between cells and the main memory.
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