Application Specific Transistor Sizing for Low Power Full Adders

Abstract

Previously suggested transistor sizing algorithms assume that all input transitions are equally important. In this work we show that this is not an accurate assumption as input transitions appear in different frequencies. We take advantage from this phenomenon and introduce Application Specific Transistor Sizing. In Application Specific Transistor Sizing higher priority is given to more frequent transitions. We apply our technique to two modern and low-power full adders (i.e., hybrid-CMOS and TFA) and show that it is possible to further reduce power dissipation and PDP. By using our technique we improve average PDP by 6% and 9% for TFA and hybrid-CMOS adders respectively. We reduce ALU energy consumption for ALU designs using TFA and hybrid-CMOS FAs by 2.7% and 4 % respectively.