2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors最新文献_第4页

Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors 生物医学植入处理器分支预测方案的评价

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.37

C. Strydis, G. Gaydadjiev

引用次数: 7

A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms 一种适用于mcelece密码系统和FPGA平台的新型处理器架构

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.29

A. Shoufan, Thorsten Wink, H. G. Molter, S. Huss, Falko Strenzke

引用次数: 35

Run-Time Detection of Malwares via Dynamic Control-Flow Inspection 基于动态控制流检测的恶意软件运行时检测

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.30

Yong-Joon Park, Zhao Zhang, Songqing Chen

引用次数: 2

Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware 在可重构硬件上实现高参数化数字PIV系统

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.20

A. Bennis, M. Leeser, G. Tadmor

{"title":"Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware","authors":"A. Bennis, M. Leeser, G. Tadmor","doi":"10.1109/ASAP.2009.20","DOIUrl":"https://doi.org/10.1109/ASAP.2009.20","url":null,"abstract":"This paper presents PARPIV the design and prototyping of a highly parameterized digital Particle Image Velocimetry (PIV) system implemented on reconfigurable hardware. Despite many improvements to PIV methods over the last twenty years, PIV post-processing remains a computationally intensive task. It becomes a serious bottleneck as camera acquisition rates reach 1000 frames per second. In this research, we aim to substantially speed up PIV processing by implementing it in reconfigurable hardware. Furthermore, this implementation is highly parameterized, supporting adaptation to a variety of setups and application domains. The circuit is parameterized by the dimensions of the captured images as well as the dimensions of the interrogation windows and sub-areas, pixel representation, board memory width, displacement and overlap. Through this work a parameterized library of different VHDL components was built. To the best of the authors’ knowledge, this is the first highly parameterized PIV system implemented on reconfigurable hardware reported in the literature. For a typical PIV configuration with images of 512×512 pixels, 40×40 pixel interrogation windows and 32×32 pixel sub-areas, we achieved about 65 times speedup in hardware over a standard software implementation.","PeriodicalId":202421,"journal":{"name":"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130426700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient Implementation of Carry-Save Adders in FPGAs fpga中免进位加法器的高效实现

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-07 DOI: 10.1109/ASAP.2009.22

J. Hormigo, M. Ortiz, F. Quiles, Francisco J. Jaime, J. Villalba, E. Zapata

{"title":"Efficient Implementation of Carry-Save Adders in FPGAs","authors":"J. Hormigo, M. Ortiz, F. Quiles, Francisco J. Jaime, J. Villalba, E. Zapata","doi":"10.1109/ASAP.2009.22","DOIUrl":"https://doi.org/10.1109/ASAP.2009.22","url":null,"abstract":"Most Field Programmable Gate Array (FPGA) devices have a special fast carry propagation logic intended to optimize addition operations. The redundant adders do not easily fit into this specialized carry-logic and, consequently, they require double hardware resources than carry propagate adders, while showing a similar delay for small size operands. Therefore, carry-save adders are not usually implemented on FPGA devices, although they are very useful in ASIC implementations. In this paper we study efficient implementations of carry-save adders on FPGA devices, taking advantage of the specialized carry-logic. We show that it is possible to implement redundant adders with a hardware cost close to that of a carry propagate adder. Specifically, for 16 bits and bigger wordlengths, redundant adders are clearly faster and have an area requirement similar to carry propagate adders. Among all the redundant adders studied, the 4:2 compressor is the fastest one, presents the best exploitation of the logic resources within FPGA slices and the easiest way to adapt classical algorithms to efficiently fit FPGA resources.","PeriodicalId":202421,"journal":{"name":"2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113975657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA MSA-CUDA:在CUDA图形处理单元上的多序列对齐

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors Pub Date : 2009-07-01 DOI: 10.1109/ASAP.2009.14

Yongchao Liu, B. Schmidt, D. Maskell

引用次数: 93