2013 23rd International Conference on Field programmable Logic and Applications最新文献_第7页

Bambu: A modular framework for the high level synthesis of memory-intensive applications Bambu:用于内存密集型应用程序的高级综合的模块化框架

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645550

C. Pilato, Fabrizio Ferrandi

引用次数: 123

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links 具有三维感应耦合链路的异构多核处理器的演示

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645628

Yusuke Koizumi, N. Miura, Yasuhiro Take, Hiroki Matsutani, T. Kuroda, H. Amano, Ryuichi Sakamoto, M. Namiki, K. Usami, Masaaki Kondo, Hiroshi Nakamura

引用次数: 0

Generation of multi-core systems from multithreaded software 从多线程软件生成多核系统

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645582

Alexander Wold, J. Tørresen, Andreas Agne

引用次数: 0

Automated synthesis of FPGA-based heterogeneous interconnect topologies 基于fpga的异构互连拓扑的自动合成

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645494

A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo

{"title":"Automated synthesis of FPGA-based heterogeneous interconnect topologies","authors":"A. Cilardo, E. Fusella, L. Gallo, A. Mazzeo","doi":"10.1109/FPL.2013.6645494","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645494","url":null,"abstract":"The choice of the communication topology in many systems is of vital importance because it affects the entire inter-component data traffic and impacts significantly the overall system performance and cost. On the other hand, there is a very large spectrum of interconnection topologies that potentially meet given communication requirements, determining various trade-offs between cost and performance. This work proposes an automated methodology to choose among all of these possibilities, avoiding a manual and time consuming design space search process. The methodology takes as input the description of the application communication requirements, and gives as output an on-chip synthesizable interconnection structure satisfying given area constraints. Targeted at FPGA technologies, the approach generates an interconnection structure combining crossbars and shared buses, connected through bridges, yielding a scalable, efficient structure. To the best of the authors' knowledge, it provides the first method to automatically generate FPGA-based communication architectures where heterogeneous communication elements, such as shared buses and crossbar switches, coexist in a network inherently supporting multiple communication paths. The resulting architecture improves the level of communication parallelism that can be exploited, while keeping area requirements low. The paper thoroughly describes the formalisms and the methodology used to derive such optimized heterogeneous topologies. It also discusses a couple of case-study applications emphasizing the impact of the proposed approach and highlighting the essential differences with a few other solutions in the literature.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121359436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Accelerating solvers for global atmospheric equations through mixed-precision data flow engine 利用混合精度数据流引擎加速求解全球大气方程

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645508

L. Gan, H. Fu, W. Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang

引用次数: 35

An open-source multi-FPGA modular system for fair benchmarking of True Random Number Generators 一个开源的多fpga模块化系统，用于真随机数生成器的公平基准测试

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645570

V. Fischer, F. Bernard, Patrick Haddad

引用次数: 14

Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation 通过LUT组态位操作提高FPGA的自主软容错性

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645498

Anup Das, Shyamsundar Venkataraman, Akash Kumar

引用次数: 15

Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS 虚拟粗粒度可重构阵列在fpga上的高效实现

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645516

Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, D. Stroobandt

引用次数: 22

Accurate and flexible flow-based monitoring for high-speed networks 准确灵活的高速网络流量监控

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645557

Marco Forconesi, G. Sutter, S. López-Buedo, J. Aracil

引用次数: 12

Energy efficient parameterized FFT architecture 节能参数化FFT架构

2013 23rd International Conference on Field programmable Logic and Applications Pub Date : 2013-10-24 DOI: 10.1109/FPL.2013.6645545

Ren Chen, H. Le, V. Prasanna

{"title":"Energy efficient parameterized FFT architecture","authors":"Ren Chen, H. Le, V. Prasanna","doi":"10.1109/FPL.2013.6645545","DOIUrl":"https://doi.org/10.1109/FPL.2013.6645545","url":null,"abstract":"In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. A parameterized FFT architecture is proposed to identify the design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize decomposition based FFT algorithms. Then we explore an energy efficient design by empirical selection on the values of the chosen architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The trade offs between energy, area, and time are analyzed using two performance metrics: the energy efficiency (defined as the number of operations per Joule) and the Energy×Area×Time (EAT) composite metric. From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N-point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127850568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22