Marco Forconesi, G. Sutter, S. López-Buedo, J. Aracil
{"title":"Accurate and flexible flow-based monitoring for high-speed networks","authors":"Marco Forconesi, G. Sutter, S. López-Buedo, J. Aracil","doi":"10.1109/FPL.2013.6645557","DOIUrl":null,"url":null,"abstract":"In this paper we present an FPGA-based architecture to export flows in 10 Gbps networks, implemented on the NetFPGA-10G platform. Flow-based monitoring is a powerful methodology to analyze and detect network issues, such as congested links or DDoS attacks. Our design provides the following advantages: (i) The architecture allows processing 10 Gbps links without sampling, even for the highest packet rate of 14.88 Mpps (Million packets per second) that corresponds to the shortest (64-byte) Ethernet frames; (ii) It is possible to manage up to 786,432 concurrent flows; (iii) The project is developed in an open-source hardware platform and the HDL code is open to the community; (iv) The proposed approach frees network routers from the burden of exporting flows.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 23rd International Conference on Field programmable Logic and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL.2013.6645557","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
In this paper we present an FPGA-based architecture to export flows in 10 Gbps networks, implemented on the NetFPGA-10G platform. Flow-based monitoring is a powerful methodology to analyze and detect network issues, such as congested links or DDoS attacks. Our design provides the following advantages: (i) The architecture allows processing 10 Gbps links without sampling, even for the highest packet rate of 14.88 Mpps (Million packets per second) that corresponds to the shortest (64-byte) Ethernet frames; (ii) It is possible to manage up to 786,432 concurrent flows; (iii) The project is developed in an open-source hardware platform and the HDL code is open to the community; (iv) The proposed approach frees network routers from the burden of exporting flows.