2022 IEEE High Performance Extreme Computing Conference (HPEC)最新文献_第4页

On the Characterization of the Performance-Productivity Gap for FPGA FPGA性能-生产率差距的表征

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926404

Atharva Gondhalekar, Thomas Twomey, W. Feng

{"title":"On the Characterization of the Performance-Productivity Gap for FPGA","authors":"Atharva Gondhalekar, Thomas Twomey, W. Feng","doi":"10.1109/HPEC55821.2022.9926404","DOIUrl":"https://doi.org/10.1109/HPEC55821.2022.9926404","url":null,"abstract":"Today, FPGA vendors provide a C++/C-based programming environment to enhance programmer productivity over using a hardware-description language at the register-transfer level. The common perception is that this enhanced pro-ductivity comes at the expense of significantly less performance, e.g., as much an order of magnitude worse. To characterize this performance-productivity tradeoff, we propose a new composite metric, II, that quantitatively captures the perceived discrepancy between the performance and productivity of any two given FPGA programming languages, e.g., Verilog vs. OpenCL. We then present the implications of our metric via a case study on the design of a Sobel filter (i.e., edge detector) using three different programming models - Verilog, OpenCL, oneAPI - on an Intel Arria 10 GX FPGA accelerator. Relative to performance, our results show that an optimized OpenCL kernel achieves 84% of the performance of an optimized Verilog version of the code on a 7680×4320 (8K) image. Conversely, relative to productivity, OpenCL offers a 6.1 x improvement in productivity over Verilog, while oneAPI improves the productivity by an additional factor of 1.25 x over OpenCL.","PeriodicalId":200071,"journal":{"name":"2022 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Explicit Ordering Refinement for Accelerating Irregular Graph Analysis 加速不规则图分析的显式排序改进

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926340

Michael Mandulak, Ruochen Hu, George M. Slota

{"title":"Explicit Ordering Refinement for Accelerating Irregular Graph Analysis","authors":"Michael Mandulak, Ruochen Hu, George M. Slota","doi":"10.1109/HPEC55821.2022.9926340","DOIUrl":"https://doi.org/10.1109/HPEC55821.2022.9926340","url":null,"abstract":"Vertex reordering for efficient memory access in extreme-scale graph-based data analysis shows considerable improvement to the cache efficiency and runtimes of widely used graph analysis algorithms. Despite this, modern efficient ordering methods are often heuristic-based and do not directly optimize some given metrics. Thus, this paper conducts an experimental study into explicit metric-based vertex ordering optimization. We introduce a universal graph partitioning-inspired approach focusing on CPU shared-memory parallelism to the vertex ordering problem through the explicit refinement of low-degree vertices using the Linear Gap Arrangement and Log Gap Arrangement problems as comprehensive metrics for ordering improvement. This degree-based refinement method is evaluated upon a number of initial orderings with timing and cache efficiency results relative to three shared-memory graph analytic algorithms: PageRank, Louvain and the Multistep algorithm. Applying refinement, we observe runtime improvements of up to 15x on the ClueWeb09 graph and up to 4x improvements to cache efficiency on a variety of network types and initial orderings, demonstrating the feasibility of an optimization approach to the vertex ordering problem at a large scale.","PeriodicalId":200071,"journal":{"name":"2022 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"73 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114092450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analyzing Multi-trillion Edge Graphs on Large GPU Clusters: A Case Study with PageRank 在大型GPU集群上分析数万亿个边缘图:以PageRank为例

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926341

Seunghwa Kang, Joseph Nke, Brad Rees

{"title":"Analyzing Multi-trillion Edge Graphs on Large GPU Clusters: A Case Study with PageRank","authors":"Seunghwa Kang, Joseph Nke, Brad Rees","doi":"10.1109/HPEC55821.2022.9926341","DOIUrl":"https://doi.org/10.1109/HPEC55821.2022.9926341","url":null,"abstract":"We previously reported PageRank performance results on a cluster with 32 A100 GPUs [7]. This paper extends the previous work to 2048 GPUs. The previous implementation performs well as long as the number of G PU s is small relative to the square of the average vertex degree but its scalability deteriorates as the number of GPUs further increases. We updated our previous implementation with the following objectives: 1) enable analyzing a P times larger graph with P times more GPUs up to P = 2048, 2) achieve reasonably good weak scaling, and 3) integrate the improvements to the open-source data science ecosystem (i.e. RAPIDS cuGraph, https://github.com/rapidsai/cugraph). While we evaluate the updates with PageRank in this paper, they improve the scalability of a broader set of algorithms in cuGraph. To be more specific, we updated our 2D edge partitioning scheme; implemented the PDCSC (partially doubly compressed sparse column) format which is a hybrid data structure that combines CSC (compressed sparse column) and DCSC (doubly compressed sparse column); adopted (key, value) pairs to store edge source vertex property values; and improved the reduction communication strategy. The 32 GPU cluster has A100 GPUs (40 GB HBM per GPU) connected with NVLink. We ran the updated implementation on the Selene supercomputer which uses InfiniBand for inter-node communication and NVLink for intra-node communication. Each Selene node has eight A100 GPUs (80 GB HBM per GPU). Analyzing the web crawl graph (3.563 billion vertices and 128.7 billion edges, 32 bit vertex ID, unweighted, average vertex degree: 36.12) took 0.187 second per Page Rank iteration on the 32 GPU cluster. Computing Page Rank scores of a scale 38 R-mat graph (274.9 billion vertices and 4.398 trillion edges, 64 bit vertex ID, 32 bit edge weight, average vertex degree: 16) took 1.54 second per Page Rank iteration on the Selene supercomputer with 2048 GPUs. We conclude this paper discussing potential network system enhancements to improve the scaling.","PeriodicalId":200071,"journal":{"name":"2022 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Online Detection and Classification of State Transitions of Multivariate Shock and Vibration Data 多元冲击与振动数据状态转换的在线检测与分类

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926361

Nicklaus Przybylski, William M. Jones, Nathan Debardeleben

引用次数: 0

Im2win: Memory Efficient Convolution On SIMD Architectures Im2win: SIMD架构上的内存高效卷积

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926408

Shuai-bing Lu, Jun Chu, X. Liu

{"title":"Im2win: Memory Efficient Convolution On SIMD Architectures","authors":"Shuai-bing Lu, Jun Chu, X. Liu","doi":"10.1109/HPEC55821.2022.9926408","DOIUrl":"https://doi.org/10.1109/HPEC55821.2022.9926408","url":null,"abstract":"Convolution is the most expensive operation among neural network operations, thus its performance is critical to the overall performance of neural networks. Commonly used convolution approaches, including general matrix multiplication (GEMM)-based convolution and direct convolution, rely on im2col for data transformation or do not use data transformation at all, respectively. However, the im2col data transformation can lead to at least 2 x memory footprint compared to not using data transformation at all, thus limiting the size of neural network models running on memory-limited systems. Meanwhile, not using data transformation usually performs poorly due to nonconsecutive memory access although it consumes less memory. To solve those problems, we propose a new memory-efficient data transformation algorithm, called im2win. This algorithm refactorizes a row of square or rectangle dot product windows of the input image and flattens unique elements within these windows into a row in the output tensor, which enables consecutive memory access and data reuse, and thus greatly reduces the memory overhead. Furthermore, we propose a high-performance im2win-based convolution algorithm with various optimizations, including vectorization, loop reordering, etc. Our experimental results show that our algorithm reduces the memory overhead by average to 41.6% compared to the PyTorch's convolution implementation based on im2col, and achieves average to 3.6 × and 5.3× speedup in performance compared to the im2col-based convolution and not using data transformation, respectively.","PeriodicalId":200071,"journal":{"name":"2022 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117236517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Achieving Speedups for Distributed Graph Biconnectivity 实现分布式图双连接的加速

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926360

Ian Bogle, George M. Slota

引用次数: 0

Accelerating Sparse Deep Neural Network Inference Using GPU Tensor Cores 利用GPU张量核加速稀疏深度神经网络推理

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926300

Yufei Sun, Long Zheng, Qinggang Wang, Xiangyu Ye, Yu Huang, Pengcheng Yao, Xiaofei Liao, Hai Jin

{"title":"Accelerating Sparse Deep Neural Network Inference Using GPU Tensor Cores","authors":"Yufei Sun, Long Zheng, Qinggang Wang, Xiangyu Ye, Yu Huang, Pengcheng Yao, Xiaofei Liao, Hai Jin","doi":"10.1109/HPEC55821.2022.9926300","DOIUrl":"https://doi.org/10.1109/HPEC55821.2022.9926300","url":null,"abstract":"Sparse deep neural networks (SpDNN) attract a lot of research and industry attention because of their powerful learning capability, whose execution time is dominated by the sparse matrix-dense matrix multiplication (SpMM). As one of specialized processors for matrix multiplication, NVIDIA GPU Tensor Cores can perform half-precision matrix-matrix multiplication with higher performance than CUDA Cores, which provides great op-portunities for SpMM acceleration. However, performing SpMM efficiently on Tensor Cores remains tremendously challenging. First, typical Tensor Cores do not handle extremely sparse matrix computations well, delivering much lower performance compared to the dense counterparts. Second, the single-precision Challenge dataset prevents them from leveraging powerful Tensor Cores to improve performance. To this end, we first propose a similarity-based matrix transformation scheme, which polarizes the weight matrix to be either denser or sparser in local regions. Then the denser and sparser workloads are respectively processed on Tensor Cores and CUDA Cores, boosting the overall efficiency. Second, considering the half-precision limitation of Tensor Cores, we further propose a lightweight emulation algorithm to achieve the single-precision computation on Tensor Cores without affecting the correctness of final results. To the best of our knowl-edge, this paper is the first to accelerate SpDNN inference on Tensor Cores without compromising the precision requirement. Extensive experiments validate that our work reaches up to 300 TeraEdges per second inference throughput on a single A100 GPU, yielding up to 89.41x and 8.12x speedups against the champions of the 2020 and 2021 Sparse Deep Neural Network Graph Challenge, respectively. Moreover, our 4-GPU version are also up to 6.56 x faster over the 2021 champion running on 4 GPUs and 7.55x faster over the 2020 champion running on 768 GPUs.","PeriodicalId":200071,"journal":{"name":"2022 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121059590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

HashTag: Fast Lookup in a Persistent Memory File System 持久内存文件系统中的快速查找

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926368

Matthew Curtis-Maury, Yash Trivedi

引用次数: 0

A Scalable Inference Pipeline for 3D Axon Tracing Algorithms 三维轴突跟踪算法的可扩展推理管道

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926403

Benjamin Fenelon, L. Gjesteby, Webster Guan, Juhyuk Park, Kwanghun Chung, L. Brattain

引用次数: 0

Surrogate ML/AI Model Benchmarking for FAIR Principles' Conformance 公平原则一致性的代理ML/AI模型基准测试

2022 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2022-09-19 DOI: 10.1109/HPEC55821.2022.9926401

P. Luszczek, Cade Brown

引用次数: 0