2018 7th Electronic System-Integration Technology Conference (ESTC)最新文献_第6页

Microfluidic Interposer for High Performance Fluidic Chip Cooling 用于高性能流控芯片冷却的微流控中间体

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546344

W. Steller, F. Windrich, D. Bremner, S. Robertson, R. Mrossko, J. Keller, T. Brunschwiler, G. Schlottig, H. Oppermann, M. Wolf, K. Lang

{"title":"Microfluidic Interposer for High Performance Fluidic Chip Cooling","authors":"W. Steller, F. Windrich, D. Bremner, S. Robertson, R. Mrossko, J. Keller, T. Brunschwiler, G. Schlottig, H. Oppermann, M. Wolf, K. Lang","doi":"10.1109/ESTC.2018.8546344","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546344","url":null,"abstract":"High operation temperatures are a main impact factor for long-term reliability. An efficient cooling approach is crucial especially for high performance computing processors (HPC). As reference, the “International Technology Roadmap for Semiconductors” (ITRS) predicted a power consumption of about 700W for data center server processors [1]. Different cooling approaches were investigated already [2]. Unfortunately, current solutions are not sufficient to fulfill high thermal HPC specifications. On one hand, the insufficient cooling performance is raising the chip junction temperature over the critical point. On other hand, the high performance requirements (e.g. low latency time, higher bandwidth) force to use 3D-Integration of components, which is additional raising the heat build-up [3, 4, 5]. Therefore, only the direct integration of a cooling approach within the 3D-stack can eliminate the overheating bottleneck at all. The fluidic cooling approach has a high potential to fulfill the requirements for this direct fluidic integration approach [6]. This work shows the integration and realization of microfluidic features (microfluidic channels and fluidic inlets/outlets) into an interposer. Furthermore we present the integration of this fluidic interposer into a System in Package (SiP) in order to realize a dual side chip cooling for a heat dissipation of 672W (168W/cm-2 which correlates with predicted power consumption of data center server processor according ITRS-Roadmap [1].","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Micro Heat Pipe Design and Fabrication on LTCC LTCC微热管的设计与制造

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546402

Malika Tlili, Maina Sinou, Camilla Kärnfelt, D. Bourreau, A. Péden

引用次数: 3

A novel TSV interposer based System-in-Package for RF applications 一种基于系统级封装的新型射频应用TSV中介器

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546492

Rongfeng Luo, Y. Chai, Shengli Ma, Xiaoyuzhang, Feng Ji, Qi Zhong

引用次数: 2

3D-Printed Eco-Friendly and Cost-Effective Wireless Platforms 3d打印环境友好，成本效益高的无线平台

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546358

Xiaochen Chen, Han He, L. Ukkonen, J. Virkki

引用次数: 4

An in-situ resistance measurement to extract IMC resistivity and kinetic parameter of alternative metallurgies for 3D stacking 采用原位电阻测量方法提取可选冶金材料三维堆垛的IMC电阻率和动力学参数

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546500

L. Hou, J. Derakhshandeh, A. Radisic, M. Honore, J. de Coster, V. Cherman, P. Bex, K. Rebibis, G. Beyer, E. Beyne, I. De Wolf

{"title":"An in-situ resistance measurement to extract IMC resistivity and kinetic parameter of alternative metallurgies for 3D stacking","authors":"L. Hou, J. Derakhshandeh, A. Radisic, M. Honore, J. de Coster, V. Cherman, P. Bex, K. Rebibis, G. Beyer, E. Beyne, I. De Wolf","doi":"10.1109/ESTC.2018.8546500","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546500","url":null,"abstract":"In this work, an in-situ resistance measurement method is proposed to investigate the interfacial solid state reaction of alternative metallurgies, such as Ni and Cu/Ni as UBM materials, with Sn solders. The electrical properties of formed IMC phases for different metallurgies systems are extracted and discussed. Kinetic parameters, such as activation energy and power factor, of Ni/Sn and Cu/Ni/Sn solid-state reaction are extracted from in-situ resistance measurement. Power factor of Ni/Sn and Cu/Ni/Sn kinetic reaction indicate that the IMC evolution behaviors involve bulk diffusion-controlled (the time exponent n = 0.5) for Ni/Sn, while the growth evolution of (Cu,Ni)6Sn5 in Cu/Ni/Sn solid state reaction involves grain-boundary diffusion controlled (the time exponent n = 0.33) from in-situ resistance measurement. This proposed in-situ measurement methodology has the advantages of being quick and accurate to understand and characterize the reaction and phase formation between UBM and solder materials for 3D applications.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Flex Cracking of Multilayer Ceramic Capacitors: Experiments on Fracture Propagation 多层陶瓷电容器的弯曲裂纹:断裂扩展实验

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546356

J. Ahmar, E. Wiss, S. Wiese

{"title":"Flex Cracking of Multilayer Ceramic Capacitors: Experiments on Fracture Propagation","authors":"J. Ahmar, E. Wiss, S. Wiese","doi":"10.1109/ESTC.2018.8546356","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546356","url":null,"abstract":"Cracking of the brittle X7R BaTiO3 ceramic dielectric material is a severe problem in areas where large sized multilayer ceramic capacitors (MLCC) are needed to provide larger capacities or higher dielectric strength for high voltage applications. Therefore the understanding of the crack formation within multilayer ceramic capacitors (MLCC) is an important issue. The paper will describe four-point-bending experiment on MLCCs, which were soldered on a pcb. The experimental design considered existing tests for the qualification of MLCC components. Basing on these considerations a specimen was designed that is able to detect the crack event via an in situ capacitance measurement. For the fabrication of the specimens two types of capacitors were chosen: MLCC 1206 and MLCC 1812. Both were made from an X7R BaTiO3 ceramic dielectric material. The substrate consisted on a 1.6 mm thick FR 4 pcb stripe having the same width as the capacitors. The capacitors were soldered using SnPbAg2, SnAg0.3Cu0.7 and SnAg3.8Cu0.7 solder alloys. After testing all samples were metallographically prepared, to analyze the cracks within the ceramic body of the capacitor by light microscopy. The paper will present the results of these microscopic studies, with regard to the crack shape that was found in the microsections of the tested specimens. The dependence of crack shape on the employed capacitor geometry and on the used solder alloy will be discussed.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123399898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi dies simultaneous bonding for power device with the newly developed pressure leveling film 动力装置多模同时粘接，采用新开发的压平膜

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546372

K. Honda, Y. Koseki, T. Ogawa, T. Nonaka

引用次数: 0

Minimizing Form Factor and Parasitic Inductances of Power Electronic Modules: The p2 Pack Technology 最小化电力电子模块的外形因数和寄生电感:p2封装技术

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/estc.2018.8546332

T. Gottwald, C. Roessle

引用次数: 1

Copper-based Graphene Nanoplatelet Composites as Interconnect for Power Electronics Pacakging 铜基石墨烯纳米板复合材料在电力电子封装中的互连研究

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546493

Jing Wang, Zhaoxia Zhou, Wen-Feng Lin, Changqing Liu, B. Ahmadi, L. Empringham

引用次数: 0

Delamination Detection in an Electronic Package by Means of a Newly Developed Delamination Chip Based on Thermal Pixel (Thixel) Array 基于热像素(thxel)阵列分层芯片的电子封装分层检测

2018 7th Electronic System-Integration Technology Conference (ESTC) Pub Date : 2018-09-01 DOI: 10.1109/ESTC.2018.8546389

Akhil Kumar, M. Schulz, S. Sheva, J. Keller, V. Bader, M. Wöhrmann, J. Bauer, D. May, B. Wunderle

{"title":"Delamination Detection in an Electronic Package by Means of a Newly Developed Delamination Chip Based on Thermal Pixel (Thixel) Array","authors":"Akhil Kumar, M. Schulz, S. Sheva, J. Keller, V. Bader, M. Wöhrmann, J. Bauer, D. May, B. Wunderle","doi":"10.1109/ESTC.2018.8546389","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546389","url":null,"abstract":"We have made advancement towards developing our novel and non-destructive system for in-situ condition monitoring and detection of delamination of interfaces within electronic packages. A matrix of $5 times 5$ solder based Thixels has been designed within each of the 4 Quadrants of a flip chip with a $10 times 10$mm2 Silicon die. Hardware layout based on a FCOB approach was designed. Before the production and assembly of the FCOB along with the testing system, a finite element study was performed to make a feasibility check by using a UBM of SiO2 on the Silicon side. Afterwards, two batches of FCOB assemblies were produced. One set with underfill and the other without. These were then tested upon a multiplexer based self-built measurement system with a software based lock-in algorithm to receive 3 omega output signals. The change in the 3 omega voltage was successfully measured in the Thixel and the results depict a good SNR at the frequency of optimum sensitivity of 500 Hz. However, we are currently able to measure one quadrant at a time and in future have the possibility to extend this to at least two, if not more. Also, with the good SNR value that has been achieved, we can further decrease the measurement time per sensor to less than 1.25 s by varying sampling parameters.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130645121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1