2020 International Wafer Level Packaging Conference (IWLPC)最新文献

{"title":"Fluxless Soldering in Activated Hydrogen Atmosphere","authors":"Gregory K. Arslanian, C. Christine Dong, R. E. Patrick, Bruce Xiang, K. Wathne","doi":"10.23919/IWLPC52010.2020.9375859","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375859","url":null,"abstract":"A novel hydrogen activation technology based on activated hydrogen or electron attachment (EA) is developed for fluxless soldering at ambient pressure and normal soldering temperature. The technology has a potential to be used for a list of applications in the electronics packaging industry and recent work by a joint effort between Air Products and Sikama International on alpha trials of a production-scale furnace for flux-free wafer bump reflow based on electron attachment (EA).","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126382205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hydrogen Embrittlement and Nano Void Classification within Electroless Copper Deposits","authors":"T. Bernhard, E. Steinhäuser, S. Kempa, G. Krilles, R. Massey, F. Brüning","doi":"10.23919/IWLPC52010.2020.9375896","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375896","url":null,"abstract":"Within the chemical reactions occurring during the deposition of electroless Copper, a low level of Hydrogen gas is evolved, and unless immediately removed, which can be problematic, is prone to accumulation on the freshly formed Cu surface. As further Cu deposition continues, the likelihood of Hydrogen encapsulation is high, and this can lead to a nonporous, low ductility Copper structure with an internal stress characteristic which leads to a high tendency for blistering. All of which are undesirable! This process is typically referred to as “Hydrogen embrittlement” and was often identified during the 1980/1990s as the probable cause for preferential failure of plated through holes in PCBs. With the development of modern electroless Copper baths, the reports of Hydrogen embrittlement related issues have been virtually eradicated, yet it is only recently that published data has offered insight into why this has occurred. As part of a larger ongoing investigation into the formation and presence of nano scaled voids within blind micro via designs, this paper reports on the impact of electrolyte stabilizers and Ni co-deposition on the occurrence and nature of Hydrogen induced voiding. Utilizing a combination of SEM, FIB and TEM techniques, it has been determined that a Ni content in excess of 30ppm in the electroless Copper solution itself, is sufficient to virtually eliminate “Hydrogen induced voids” within the resulting Copper deposit. For the single component stabilizer additives investigated, much as expected, all were found to have a positive effect in terms of grain refinement, yet, when compared to the effect arising from Ni codeposition, they were all unable to fully suppress the reduction of Hydrogen induced voids. With this further understanding, the paper concludes by identifying, classifying and offering route cause formation mechanisms for a range of nano void types that have been observed as part of these investigations as well as routine analysis on failed micro via assembles, all of which is believed to be vital in determining the best solution for void reduction across BMV interfaces and so, maximizing joint reliability.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116592012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing X-Ray Inspection for Advanaced Packaging Applications","authors":"B. Peterson, M. Kwan, F. Duewer, Andrew Reid, Rhiannon Brooks","doi":"10.23919/IWLPC52010.2020.9375900","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375900","url":null,"abstract":"Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” In the early years, this integration happened at the system level: GPU cards, sound cards, match coprocessors, and communication devices. In the 2000's, this switched to integration of major components on die. And now, the same concept returns in integration on the local interconnect level. Figure 1 shows an example (future) device: there are large bumps, hybrid bonds−−for extreme bandwidth and low latency connection to cache memory, TSV based DRAM, and multiple CPU to CPU interconnects. Each of these is a failure point. Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. Local bandwidth has expanded by 10x, which gives rise to 10x higher pincounts. Similarly, lower latency requirements require small, low delay interconnects. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in packageinspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year at (tens of) thousands of bumps per device. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. This does require rethinking some basic assumptions in the design of semiconductor inspection systems. To take advantage of this speed, fully automated systems are needed to identify and classify defects found at th bump level. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115455363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Selective Copper Metallization for Advanced Packaging","authors":"R. Mavliev, R. Rhoades","doi":"10.23919/IWLPC52010.2020.9375858","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375858","url":null,"abstract":"Interconnects are one of the most difficult steps in the manufacturing process, particularly at advanced process nodes with more metal layers to connect, both internally and externally. The Cu damascene process is widely applied in BEOL of IC industry for interconnect formation while conventional Cu electrochemical deposition (ECD) approach is standard process flow in the packaging area. Conventional Cu ECP has low cost but has limitation on the width of line/space, the process cost will dramatically increase for smaller pitches. At same time, the shrinkage of line/space cannot be prevented with device density increasing. The Cu damascene process can easily achieve sub-micron line/space, it is the dominant interconnect technology for advanced semiconductor chip manufacturing. In a traditional process, trenches and via in dielectric layers are filled by ECD of copper followed by chemical mechanical planarization (CMP) for removal of the metal from field areas of the wafer, CMP has been an enabling technology for the use of copper in damascene technology. It has rapidly become one of the most important and widespread processes, also very costly one. For this application and for any similar process sequence, substantial savings are possible if the metal could be deposited in a selective manner and focused primarily into the features of interest rather than following the traditional inefficient approach of depositing a blanket layer. A novel method for selective deposition (Selectroplating®) has been developed and evaluated for several types of metallization applications. This technology is based on a selective chemical modification (SCM) of field areas of a wafer or substrate and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent metal from being deposited in areas between desired features thus eliminating the need to remove excess bulk in the next step. Cost savings are realized in two ways: 1) less metal is consumed from the plating bath thus extending bath life and lowering the average deposition cost, and 2) substantially less bulk metal must be removed in the subtractive step which lowers the polish or etch time. This improves throughput and further decreases cost.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128365507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Process & Methodology for Achieving High-Volume Production Quality for FOWLP Packaging","authors":"Keith Felton, J. Ferguson","doi":"10.23919/IWLPC52010.2020.9375892","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375892","url":null,"abstract":"With the economics of transistor scaling no longer universally applicable, the semiconductor industry is turning to innovative packaging technologies to support system scaling and functionality demands while achieving lower system cost. However, high-density packages such as fan-out wafer-level packaging (FOWLP) bring design challenges that traditional organic laminate processes and design tools struggle with and often fail to satisfy. In this paper, we address the challenges that FOWLP and similar high-density advanced packaging (HDAP) technologies bring to designers, outsourced semiconductor assembly and test (OSAT) suppliers, and foundries, and explain why traditional design processes, flows and even design tools struggle and often fail to achieve high-volume production. We discuss the innovative processes and design techniques that must be adopted not just to comply with design requirements, but to do so in a reliable, productive way to achieve high-quality results that meet manufacturing volume yield expectations. We discuss the processes and design flow Mentor developed through partnerships with leading foundries and OSATs, and how they are being used to drive high-volume production.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115774007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Construction of Rf-Blocks in Package Technologies","authors":"Fabian Hopsch, R. Trieb, A. Heinig","doi":"10.23919/IWLPC52010.2020.9375897","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375897","url":null,"abstract":"Advanced packages are necessary to cope with the requirements of 5G and radar technologies with 60 GHz and beyond. For proper RF design with rising package technology requirements demands for usage of predefined structures with predefined layout elements, manufactured and measured elements. This paper deals with an approach to have such elements available to build advanced types of packages in shorter time compared to classical approaches. The approach is a general approach but it is demonstrated with an advanced two-level package-on-package technology with a leading-edge IC technology. It is also used explain the build-up of a construction kit of RF -blocks from the design phase of test structures up to measurement of such structures, qualification and model building. From the test structure more general structures can be derived and used in the design of future 5G applications. This enables better time-to-market, reduces cost and provides higher design validation in terms of first time right.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon Die Bonding using a Photostructurable Adhesive Material","authors":"K. Hollstein, K. Weide-Zaage","doi":"10.23919/IWLPC52010.2020.9375868","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375868","url":null,"abstract":"For a novel packaging application, a method is needed to bond silicon chips on a wafer surface. One of the main requirements is a comparably thin and structurable adhesive layer. The adhesive layer has to have a thickness of approximately 10 to 20 μm and is required to cover the edges of the silicon die. As this application is quite unique, thorough research has been done to identify applicable materials and processes. Common technologies like die bonding, pin transfer, jetting etc. cannot be used as the adhesive volume has to be controlled very precise and the dimensions of the adhesive bond are too coarse for the application. The desired thickness of the adhesion layer can only be achieved using photostructurable materials. A parameter analysis has been done in order to determine applicability of the photostructurable material as an adhesive layer. Therefore, die bonding temperature and bonding pressure have been varied. The influence of the parameter variation has been demonstrated using die shear testing and cross sectional imaging. Two geometrical variations of the adhesive layer are compared. A sufficient parameter set could be identified using this approach.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132209985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Through Glass VIAS using an Industry Compatible Glass Handling Solution","authors":"D. Levy, S. Nelson, A. Shorey","doi":"10.23919/IWLPC52010.2020.9375854","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375854","url":null,"abstract":"Thin glass (≤ 200 μm) has ideal properties for electronic packaging and RF applications. In electronic packaging, a smooth, dimensionally stable surface allows high resolution line/space patterning, while through glass via (TGV) technology permits integration in many relevant packaging structures. These capabilities combine with a low loss tangent at microwave frequencies and robustness to temperature and humidity to yield high performance for RF applications. In this paper we discuss a thin glass handling solution coupled with recent innovations that give glass an entry point into these applications at large scale using existing fabrication infrastructure. Our new polymer-free bonding process allows glass to be temporarily bonded to a handle such as silicon or other glass substrates. The Viaffirm™ bonding material is non-outgassing and capable of handling temperatures in excess of 400°C while remaining temporary. When silicon is used as the handle, the opacity and form factor of the silicon substrate means that the resulting bonded stack is compatible with existing silicon processing equipment. We discuss the properties of our bonding system including temperature performance, tunability of the bond energy for different applications, and approaches to debonding. We also describe the formation and metallization of TGVs utilizing our proprietary process. When using a silicon wafer as the handle substrate, vias in the glass terminate on the silicon and are thus comparable to blind vias in silicon. We discuss the ability to make tapered TGVs while tuning their size and via profile, as well as results in metallization to produce fully filled, void free vias using a range of seed and plating approaches.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cure Process Impact on Cure Time and Properties of Low Temperature Polyimide for 3D Stacking Applications","authors":"Z. Karim, K. Sautter, Kay Song, C. Galande, K. Singh","doi":"10.23919/IWLPC52010.2020.9375874","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375874","url":null,"abstract":"In this paper, to meet the requirements of low thermal budget for 3D integration on fan-out wafer or panel level processing or on even bigger substrates such as Gen3.5 or above, thermal, mechanical, and dielectric properties were studied for a low temperature polyimide material as a function of cure parameters at a cure temperature of ~200°C under atmospheric and sub-atmospheric process conditions. These results are compared to a conventional higher temperature polyimide. Vacuum cure of low temperature polyimide appears to improve the outgassing properties and dielectric strength at lower pressure; however, the dissipation factor resulted in a higher value compared to that of conventional higher temperature polyimide. These results are consistent with the assumption that at reduced pressure, water and solvent are drawn out of the bulk polymer at much lower temperatures than an atmospheric pressure cure; however, cross-linker remains in the low temperature films during the curing process.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EMI Shielding for System in Package using Nozzle-Less Ultrasonic Spray Coating and Silver Particle Free Ink","authors":"S. Erickson, G. McKerricher, Sima Hannani, M. LeMieux","doi":"10.23919/IWLPC52010.2020.9375863","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375863","url":null,"abstract":"There is a constant drive to pack electronics into smaller spaces. Recently, smart watches have been major drivers of further miniaturization and spurred System in Package “SIP” innovations. SIP enables several integrated circuits (ICs) along with larger capacitors/inductors to be housed in one package. Many of these ICs operate at radio frequencies and the proximity increases electromagnetic interference (EMI). The traditional solution of soldering a “metal can” is not feasible. Compartmental shielding of the package is necessary and sputtered metal has typically been utilized to provide the shield. The traditional sputtering method is a Physical Vapor Deposition process (PVD) that involves vaporizing a metal and depositing it onto the surfaces of the components. PVD is currently the most commonly used method to apply the EMI shield and it requires a complex, multi -step process. New materials and application methods are required to increase performance and reduce costs associated with producing an effective EMI shield. The EMI shield layer must be applied in a uniform layer on the package surfaces and into the trenches between compartments. This paper demonstrates the capability of a revolutionary particle- free silver ink in conjunction with a novel coating application technology in the form of a nozzle-less ultrasonic spray technology and digital dispensing technology. Performance parameters including coating thickness uniformity, EMI shielding effectiveness, adhesion, process cost will be compared and analyzed between this approach and other silver inks and application methods. Results of these analyses will be presented along with performance improvement and cost reduction potential of this technique for high-volume manufacturing.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}