Selective Copper Metallization for Advanced Packaging

R. Mavliev, R. Rhoades
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Abstract

Interconnects are one of the most difficult steps in the manufacturing process, particularly at advanced process nodes with more metal layers to connect, both internally and externally. The Cu damascene process is widely applied in BEOL of IC industry for interconnect formation while conventional Cu electrochemical deposition (ECD) approach is standard process flow in the packaging area. Conventional Cu ECP has low cost but has limitation on the width of line/space, the process cost will dramatically increase for smaller pitches. At same time, the shrinkage of line/space cannot be prevented with device density increasing. The Cu damascene process can easily achieve sub-micron line/space, it is the dominant interconnect technology for advanced semiconductor chip manufacturing. In a traditional process, trenches and via in dielectric layers are filled by ECD of copper followed by chemical mechanical planarization (CMP) for removal of the metal from field areas of the wafer, CMP has been an enabling technology for the use of copper in damascene technology. It has rapidly become one of the most important and widespread processes, also very costly one. For this application and for any similar process sequence, substantial savings are possible if the metal could be deposited in a selective manner and focused primarily into the features of interest rather than following the traditional inefficient approach of depositing a blanket layer. A novel method for selective deposition (Selectroplating®) has been developed and evaluated for several types of metallization applications. This technology is based on a selective chemical modification (SCM) of field areas of a wafer or substrate and can be implemented for either a fill-based integration, such as Cu dual damascene, or an additive process such as plating of wide conductive lines. In either integration, the primary benefit of selective deposition is to prevent metal from being deposited in areas between desired features thus eliminating the need to remove excess bulk in the next step. Cost savings are realized in two ways: 1) less metal is consumed from the plating bath thus extending bath life and lowering the average deposition cost, and 2) substantially less bulk metal must be removed in the subtractive step which lowers the polish or etch time. This improves throughput and further decreases cost.
先进封装的选择性铜金属化
互连是制造过程中最困难的步骤之一,特别是在内部和外部需要连接更多金属层的高级工艺节点上。Cu damascene工艺广泛应用于集成电路工业的BEOL互连形成,而传统的Cu电化学沉积(ECD)方法是封装领域的标准工艺流程。传统的Cu ECP成本低,但受线宽/空间的限制,小间距的工艺成本将急剧增加。同时,随着器件密度的增加,线/空间的收缩是不可避免的。Cu damascene工艺可以很容易地实现亚微米线/空间,是先进半导体芯片制造的主导互连技术。在传统工艺中,电介质层中的沟槽和通孔是由铜的ECD填充的,然后是化学机械平面化(CMP),以从晶圆片的现场区域去除金属,CMP已经成为在damascene技术中使用铜的一种使能技术。它已迅速成为最重要和最广泛的工艺之一,但也非常昂贵。对于这种应用和任何类似的工艺序列,如果金属能够以选择性的方式沉积,并且主要集中在感兴趣的特征上,而不是遵循传统的低效的沉积毯层的方法,则可以节省大量资金。一种新的选择性沉积方法(selectro镀®)已经开发并评估了几种类型的金属化应用。该技术基于对晶圆或衬底区域的选择性化学修饰(SCM),可以实现基于填充的集成,例如Cu双damascene,也可以实现添加剂工艺,例如镀宽导电线。在任何一种集成中,选择性沉积的主要好处是防止金属沉积在所需特征之间的区域,从而消除了在下一步中去除多余体积的需要。成本节约通过两种方式实现:1)从镀液中消耗更少的金属,从而延长镀液寿命并降低平均沉积成本;2)在减法步骤中必须去除的大块金属大大减少,从而缩短了抛光或蚀刻时间。这提高了吞吐量并进一步降低了成本。
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