Optimizing X-Ray Inspection for Advanaced Packaging Applications

Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” In the early years, this integration happened at the system level: GPU cards, sound cards, match coprocessors, and communication devices. In the 2000's, this switched to integration of major components on die. And now, the same concept returns in integration on the local interconnect level. Figure 1 shows an example (future) device: there are large bumps, hybrid bonds−−for extreme bandwidth and low latency connection to cache memory, TSV based DRAM, and multiple CPU to CPU interconnects. Each of these is a failure point. Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. Local bandwidth has expanded by 10x, which gives rise to 10x higher pincounts. Similarly, lower latency requirements require small, low delay interconnects. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in packageinspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year at (tens of) thousands of bumps per device. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. This does require rethinking some basic assumptions in the design of semiconductor inspection systems. To take advantage of this speed, fully automated systems are needed to identify and classify defects found at th bump level. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.