2015 Conference on Design of Circuits and Integrated Systems (DCIS)最新文献_第2页

Piezoelectric harvester-based self-powered adaptive circuit with wireless data transmission capability for structural health monitoring 结构健康监测中具有无线数据传输能力的压电收割机自适应供电电路

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388594

Albert Álvarez-Carulla, J. Colomer-Farrarons, J. López-Sánchez, P. Miribel-Català

引用次数: 5

Fast radiation monitoring in FPGA-based designs 基于fpga的快速辐射监测设计

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388590

C. Leong, J. Semião, M. Santos, I. Teixeira, J. P. Teixeira, A. Batista, B. Gonçalves, J. Marques

{"title":"Fast radiation monitoring in FPGA-based designs","authors":"C. Leong, J. Semião, M. Santos, I. Teixeira, J. P. Teixeira, A. Batista, B. Gonçalves, J. Marques","doi":"10.1109/DCIS.2015.7388590","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388590","url":null,"abstract":"In nanoscale FPGAs, variability, aging and radiation effects significantly limit system performance and reliability, which is a relevant problem in safety-critical applications associated with long life operation products. The impact of Single Event Upsets (SEU) on system correct operation is usually estimated by the FPGA vendor. In this paper a technique for fast radiation monitoring, taking aging effects into account is proposed for FPGA-based designs. In order to monitor SEU in memory, a novel SEU sensor is proposed, reusing BRAM resources to estimate the Soft Error Rate (SER). The proposed BRAM-based sensor allows a much faster evaluation of radiation effects than the one obtained with traditional monitoring such as monitoring of the FPGA configuration memory. Simultaneous use of aging and SEU sensors enables the activation of mitigation techniques, e.g., circuit reconfiguration for a more robust functionality. Simulation and experimental results are presented, using Virtex6 and Spartan6 boards and two real-world applications - a data acquisition system for PET-based medical imaging, and a fast plant system controller for the ITER reactor. Neutron radiation tests were performed- in the Portuguese Research Reactor (RPI).","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116757542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

DC-DC converter power stage with cascoded transistors and automatic dead time generation 具有级联晶体管和自动死区产生的DC-DC变换器功率级

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388560

I. Filanovsky, J. Jarvenhaara, N. Tchamov

引用次数: 0

A low-power fully integrated CMOS RF receiver for 2.4-GHz-band IEEE 802.15.4 standard 2.4 ghz频段IEEE 802.15.4标准的低功耗全集成CMOS射频接收器

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388563

S. Mateos-Angulo, D. Mayor-Duarte, S. Khemchandani, J. del Pino

引用次数: 7

Compact wide-range sinusoidal signal generator for in vivo Impedance Spectroscopy 紧凑的宽范围正弦信号发生器体内阻抗谱

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388593

M. Nawito, H. Richter, J. Burghartz

引用次数: 3

System level methodology based on VIPPE applied to the implementation of a scalable video decoder on the ZynQ platform 基于VIPPE的系统级方法应用于ZynQ平台上可扩展视频解码器的实现

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388604

Abelardo Baez Quevedo, G. Callicó, S. López, J. López, R. Sarmiento, Alejandro Nicolás, P. Sánchez, E. Villar

{"title":"System level methodology based on VIPPE applied to the implementation of a scalable video decoder on the ZynQ platform","authors":"Abelardo Baez Quevedo, G. Callicó, S. López, J. López, R. Sarmiento, Alejandro Nicolás, P. Sánchez, E. Villar","doi":"10.1109/DCIS.2015.7388604","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388604","url":null,"abstract":"One of the first problems that a hardware designer needs to solve when facing a new and complex electronic design, is to know in advance where the critical parts of the design are, and how many resources the design will require. This information will ease the developing of feasible systems and will help in the design of well suited architectures. The Open SVC (Scalable Video Coding) Decoder (OSD) is an open source system created at IETR/INSA at Rennes that implements a SV decoder written in language. The scalable video encoder supposes an important overload compared with its counterpart non-scalable video encoder, which inherently already exhibits a very high computational load. Due to the huge number of functions that form part of the SV video decoder, a set of internal modules that better describes the internal structure of the decoder has been defined. In this scenario, two aspects have been selected to be the critical ones: the computational load and the transaction of data. In order to adopt appropriate decisions related with the system implementation.. This paper presents a methodology based on VIPPE that will be used to perform the profiling of a complex system like the OSD over a user-defined platform, the ZynQ from Xilinx in this case, composed by two ARM cores and an FPGA. The profiling results will guided the implementation of the OSD on the aforementioned ZynQ platform. The methodology can be easily extrapolated to any other complex design.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125847163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Interconnection coupling on lightly doped substrate for millimeter wave frequencies 毫米波频率下轻掺杂衬底的互连耦合

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388559

V. Gerakis, A. Hatzopoulos

引用次数: 0

Dependability in FPGAs, a Review fpga的可靠性综述

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388570

Igor Villalta, U. Bidarte, Julen Gomez-Cornejo, Jesús Lázaro, C. Cuadrado

引用次数: 6

Defeating Simple Power Analysis attacks in cache memories 在缓存存储器中击败简单的功率分析攻击

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388557

M. Neagu, L. Miclea, S. Manich

引用次数: 2

Towards Project-Based Learning applied to the Electronic Engineering studies 项目式学习在电子工程研究中的应用

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388615

D. Morales, E. Castillo, L. Parrilla, A. García, A. Otín

引用次数: 10