具有级联晶体管和自动死区产生的DC-DC变换器功率级

I. Filanovsky, J. Jarvenhaara, N. Tchamov
{"title":"具有级联晶体管和自动死区产生的DC-DC变换器功率级","authors":"I. Filanovsky, J. Jarvenhaara, N. Tchamov","doi":"10.1109/DCIS.2015.7388560","DOIUrl":null,"url":null,"abstract":"The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DC-DC converter power stage with cascoded transistors and automatic dead time generation\",\"authors\":\"I. Filanovsky, J. Jarvenhaara, N. Tchamov\",\"doi\":\"10.1109/DCIS.2015.7388560\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.\",\"PeriodicalId\":191482,\"journal\":{\"name\":\"2015 Conference on Design of Circuits and Integrated Systems (DCIS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Conference on Design of Circuits and Integrated Systems (DCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCIS.2015.7388560\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS.2015.7388560","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

提出了一种具有自动死区产生功能的级联功率级。该电路使用级联码结构的晶体管间节点电压作为反馈控制信号来延迟功率晶体管的导通。该电路设计为全集成降压变换器的输出级。描述了稳态运行。在45 nm CMOS工艺上模拟的波形表明,在稳态工作时避免了短路路径和本体二极管导通,同时为地线和电源线提供了有效的零电压开关(ZVS);计算的死区时间与仿真结果吻合较好。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
DC-DC converter power stage with cascoded transistors and automatic dead time generation
The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信