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2015 Conference on Design of Circuits and Integrated Systems (DCIS)最新文献

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A self-tuned thermal compensation system for reducing Process Variation influence in side-channel attack resistant dual-rail logic 一种自调谐热补偿系统，用于降低工艺变化对抗侧通道攻击的双轨逻辑的影响
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388574
Wei He, M. Stottinger, E. de la Torre, Veronica Diaz
{"title":"A self-tuned thermal compensation system for reducing Process Variation influence in side-channel attack resistant dual-rail logic","authors":"Wei He, M. Stottinger, E. de la Torre, Veronica Diaz","doi":"10.1109/DCIS.2015.7388574","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388574","url":null,"abstract":"Dual-rail Precharged Logic (DPL) theoretically withstands Side-Channel Attacks owing to its physical-level compensation manner between the tailored complementary rails. However, the security grade of DPLs can be severely impaired by the innate silicon Process Variation (PV), even the two rails are identically constructed. In this paper, an active thermal compensation system is presented to alleviate the PV-relevant security tension for SCA-resistant dual-rail logic. The devised system consists of a Ring-Oscillator (RO) based temperature sensor pair and two groups of heat generators, respectively scaled with each of the complementary crypto cores. The heaters are automatically switched on in accordance to the frequency difference measured by the ROs. The more secure compensation is achieved by tuning the local thermal to the one wherein higher RO frequency is detected, for affecting the local electrical characteristics to slow down the higher frequency. The protocol of the system and the implementation flow are detailed in this paper. The security verifications are validated by employing the RO thermal system to a lightweight crypto coprocessor in its identical dual-rail format. The experiment results certified elevated security grade to the crypto cores on Virtex-5 FPGA when the thermal compensation system is switched on.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124523539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers 基于相关形状区分符的Trivium流密码优化DPA攻击
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388578
E. Tena-Sánchez, A. Acosta
{"title":"Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers","authors":"E. Tena-Sánchez, A. Acosta","doi":"10.1109/DCIS.2015.7388578","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388578","url":null,"abstract":"Trivium is a hardware oriented stream cipher finalist of the eSTREAM project. In this work, an optimized Differential Power Analysis (DPA) attack on Trivium using correlation shape distinguishers is presented. Unlike in the previous reported attacks, we are able to retrieve the whole 80-bit key without making any hypothesis during the attack using the proposed method. The theoretical vulnerability analysis is presented and then checked developing a simulation-based DPA attack on a standard CMOS Trivium implementation in a 90nm TSMC technology. The results show that our simulation-based attack is successful for random keys, improving the previously-reported attacks at least in 91.25% in terms of number of patterns needed to recover the key.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121129923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Construction of a quadcopter for autonomous and teleoperated navigation 构建用于自主和远程操作导航的四轴飞行器
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388600
V. Andaluz, Fernando A. Chicaiza, A. Meythaler, D. Rivas, Cristian P. Chuchico
{"title":"Construction of a quadcopter for autonomous and teleoperated navigation","authors":"V. Andaluz, Fernando A. Chicaiza, A. Meythaler, D. Rivas, Cristian P. Chuchico","doi":"10.1109/DCIS.2015.7388600","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388600","url":null,"abstract":"This work presents the construction and autonomous and tele-operated control of a miniature quadcopter for applications in confined spaces, more specifically in corridors, both indoor and outdoor. Furthermore, the development of a Human Machine Interface that simulates the behavior of the UAV to different control strategies, and performs two-way communication between the ground station and the quadcopter is presents. Finally, real experiments results are presented and discussed, which validate the construction of the UAV and the proposed controller.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129601348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis of teaching methodologies for electronics in non-specialized engineering studies 非专业工程研究中的电子学教学方法分析
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7491915
Y. Lechuga, M. Martinez, R. Casanueva
{"title":"Analysis of teaching methodologies for electronics in non-specialized engineering studies","authors":"Y. Lechuga, M. Martinez, R. Casanueva","doi":"10.1109/DCIS.2015.7491915","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7491915","url":null,"abstract":"Since the academic year 2011-2012, the Electronics courses have started to be taught within the curriculum of the new Degree in Mechanical Engineering and the new Degree in Electrical Engineering, which are part of the undergraduate academic offer of the University of Cantabria (Spain). Both courses follow a common teaching and learning methodology regarding, not only the syllabus contents and organization, but also the assessment of competencies. During four academic years, changes in the course syllabus have been done, as well as different assessment procedures have been developed and analysed. In this way, the teachers of these two courses have been able to evaluate the extent to which students have acquired the expected competencies and also to draw conclusions about the most suited learning methodology to both student profiles, with the specific objective of decreasing the dropout rate.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131152412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FPGA implementation of SVPWM approximation SVPWM逼近的FPGA实现
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388572
Salim Boukaka, D. Massicotte, P. Sicard
{"title":"FPGA implementation of SVPWM approximation","authors":"Salim Boukaka, D. Massicotte, P. Sicard","doi":"10.1109/DCIS.2015.7388572","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388572","url":null,"abstract":"The PWM signal generator is a key element in DC-AC conversion and AC drives. A new scheme based on the approximation of Space Vector Pulse Width Modulation is proposed to minimize the mathematical complexity involved with the SVPWM, while retaining its advantages. The proposition has been implemented on FPGA using Hardware Description Language VHDL and its co-simulation with Simulink™/Matlab®. The new implementation consumes about 30% of the resources of the conventional method for synthesis using ISE Xilinx Design software on a Spartan3 Platform.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130095768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs 非均匀分路电容阵列SAR adc中电容非理想性的影响
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388595
R. Fiorelli, O. Guerra, R. del Río, Á. Rodríguez-Vázquez
{"title":"Effects of capacitors non-idealities in un-even split-capacitor array SAR ADCs","authors":"R. Fiorelli, O. Guerra, R. del Río, Á. Rodríguez-Vázquez","doi":"10.1109/DCIS.2015.7388595","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388595","url":null,"abstract":"This paper studies the effects of capacitors non-idealities in the performance of un-even split-capacitor SAR ADCs. Also, election of the m and l bits of MSB and LSB capacitors banks, respectively, is studied to reduce SAR errors. To exemplify and quantify the non-idealities, MOM capacitors are used. In particular, MOM layout parasitics and effective capacitors' value is obtained with an electrical extraction tool using a flattened view of the MOM. Effects of capacitors layout placement in the SAR and their surroundings in the effective capacitance value are quantified. A quantitative study of a 10-bit un-even split-capacitor SAR is done for different combinations of m and l bits. Finally, a qualitative set of guidelines to choose the distribution of these bits is listed.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123072548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of a high efficiency GaN-HEMT RF power amplifier 高效GaN-HEMT射频功率放大器的设计
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388610
Nagavenkat K. Gaddam, J. Machado da Silva
{"title":"Design of a high efficiency GaN-HEMT RF power amplifier","authors":"Nagavenkat K. Gaddam, J. Machado da Silva","doi":"10.1109/DCIS.2015.7388610","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388610","url":null,"abstract":"This paper presents the design and implementation of a GaN-HEMT, class-J power amplifier suitable for cognitive radio transceivers, i. e., which presents high-efficiency and wideband characteristics, being these maintained for large load variations. Simulation results are presented which show large-signal measurement results of 30 dB gain with 60%-76% power-added efficiency (PAE) over a band of 1.3-2.3 GHz. Adaptivity to load changes is being developed to ensure PAE above 70% for large load variations.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121944672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Joint decision-directed beamforming and channel equalization approach for OFDM systems OFDM系统的联合决策定向波束形成和信道均衡方法
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388603
Chih-Feng Wu, Chun-Hung Chen
{"title":"Joint decision-directed beamforming and channel equalization approach for OFDM systems","authors":"Chih-Feng Wu, Chun-Hung Chen","doi":"10.1109/DCIS.2015.7388603","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388603","url":null,"abstract":"In this paper, a joint decision-directed beamforming and channel equalization approach is presented for OFDM systems in the presence of co-channel interference (CCI). According to the minimum mean-square error (MMSE) criterion, the cost function of the joint approach is proposed to minimize the MSE on each subchannel and to further improve the system performance. The joint approach is a dual-loop structure composed of a beamforming and a channel equalization loops. The beamforming loop is primarily employed to suppress CCI. The channel equalization loop is used to compensate the baseband equivalent channel variations caused by multipath fading channel and adaptation of beamformer. The simulations are done for the multipath frequency-selective fading channel with CCI to show that the proposed approach can effectively eliminate CCI and compensate the channel distortions, thereby enhancing the system performance compared with the considered pilot-aided approach.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
UML-based single-source approach for evaluation and optimization of mixed-critical embedded systems 基于uml的混合关键嵌入式系统评估与优化的单源方法
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388565
P. Peñil, H. Posadas, J. Medina, E. Villar
{"title":"UML-based single-source approach for evaluation and optimization of mixed-critical embedded systems","authors":"P. Peñil, H. Posadas, J. Medina, E. Villar","doi":"10.1109/DCIS.2015.7388565","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388565","url":null,"abstract":"Mixed-critical systems combine highly-critical tasks with non-critical activities. Among them, there is a trend of sharing the available HW resources for all these activities, as a way of optimizing costs and power consumption. However, the design of such complex systems is a challenge, due to the different requirements and goals of critical and non-critical tasks, and the side effects resulting from their integration. As a consequence, the design of mixed critical systems requires the integration of different design flows and tools, and consideration of the whole system during the development of each specific component. To handle this challenge, this paper presents a single-source proposal where UML models are used as a common input that drives a flow of different design tools in a mixed-critical context. The flow covers performance estimation, static schedulability analysis and code synthesis to guarantee the critical tasks' constraints and to evaluate the remaining times available for the execution of non-real time tasks.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127266806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology 基于180nm CMOS技术的环形压控振荡器锁相环稳定脉冲发生器系统的设计
2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388576
G. Blasco, E. Isern, E. Martin
{"title":"Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology","authors":"G. Blasco, E. Isern, E. Martin","doi":"10.1109/DCIS.2015.7388576","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388576","url":null,"abstract":"We have designed system for the generation of stable pulses, with controllable pulse width, by means of a Ring-VCO Phase-Locked Loop (PLL) and a secondary Ring Oscillator, developed in standard 180nm CMOS technology. The PLL is a Charge-Pump PLL (CPPLL) with a passive third order Loop Filter (LF) and a Ring-VCO. The VCO controls two identical ring oscillators (RO), each one based on 41 single-ended inverters having multiple-phase output. The first RO is included in the PLL function, while the second RO is used for the pulse generation. The PLL has a pull-in range from 28MHz to 125MHz, and the system generates stable pulses having widths going from 500 ps up to 5 ns. Simulations and jitter calculations are provided. Results of final physical implementation are included together with laboratory measurements.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133915031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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