Design of a stable pulse generator system based on a Ring-VCO Phase-Locked Loop using 180nm CMOS technology

Abstract

We have designed system for the generation of stable pulses, with controllable pulse width, by means of a Ring-VCO Phase-Locked Loop (PLL) and a secondary Ring Oscillator, developed in standard 180nm CMOS technology. The PLL is a Charge-Pump PLL (CPPLL) with a passive third order Loop Filter (LF) and a Ring-VCO. The VCO controls two identical ring oscillators (RO), each one based on 41 single-ended inverters having multiple-phase output. The first RO is included in the PLL function, while the second RO is used for the pulse generation. The PLL has a pull-in range from 28MHz to 125MHz, and the system generates stable pulses having widths going from 500 ps up to 5 ns. Simulations and jitter calculations are provided. Results of final physical implementation are included together with laboratory measurements.