2015 Conference on Design of Circuits and Integrated Systems (DCIS)最新文献_第6页

Implementation of a zero-second-IF transmitter for wide-band millimeter-wave links 用于宽频带毫米波链路的零秒中频发射机的实现

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388575

Ainhoa Rezola, Aritz Alonso, J. F. Sevillano, Iñaki Gurutzeaga, R. Berenguer, I. Vélez

引用次数: 4

Digital pseudorandom uniform noise generators for ADC histogram test 用于ADC直方图测试的数字伪随机均匀噪声发生器

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388592

Jose Domingos Alves, G. Evans

引用次数: 5

Quantitative modelling of image processing algorithms for hardware implementation 定量建模的图像处理算法的硬件实现

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388569

T. Szydzik, G. Callicó, A. Núñez

引用次数: 0

FPGA implementation of a library of adaptive control laws for PMSM FPGA实现的永磁同步电机自适应控制律库

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388573

Salim Boukaka, Hakim Teiar, P. Sicard

引用次数: 0

Embedding Fault List Compression techniques in a design automation framework for analog and Mixed-Signal structural testing 在模拟和混合信号结构测试的设计自动化框架中嵌入故障表压缩技术

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388584

R. Martins, N. Lourenço, N. Horta, N. Guerreiro, Marcelino B. Santos

{"title":"Embedding Fault List Compression techniques in a design automation framework for analog and Mixed-Signal structural testing","authors":"R. Martins, N. Lourenço, N. Horta, N. Guerreiro, Marcelino B. Santos","doi":"10.1109/DCIS.2015.7388584","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388584","url":null,"abstract":"The innovative work “Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression” [1] focuses on the prohibitive number of structural faults which need to be simulated, at circuit-level, in the design environment. It proposes a fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. The methodology allows different tradeoffs between fault list compression and fault representation accuracy by changing the number of strata, L. These concepts are embed them in the AIDA's framework [2][3], which is an analog IC design automation environment, and, allows the designer to select a circuit sizing and determine an efficient set of stimuli for fault detection, reducing the simulations required in the test environment. A single ended 2-stage amplifier is used here to demonstrate the proposed developments in the field of structural testing. All the results are presented for the United Microelectronics Corporation (UMC) 130 nanometers technology node.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"62 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A 40.9 µW high sensitivity wake-up radio for wireless sensor networks using uncertain-IF architecture 采用不确定中频架构的40.9µW高灵敏度无线传感器网络唤醒无线电

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388585

Emilio Torres Armas, D. Ramos-Valido, S. Khemchandani, J. del Pino

引用次数: 4

A fast and configurable architecture for Discrete Wavelet Packet Transform 离散小波包变换的快速可配置结构

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2015-11-01 DOI: 10.1109/DCIS.2015.7388599

Mouhamad Chehaitly, M. Tabaa, F. Monteiro, A. Dandache

{"title":"A fast and configurable architecture for Discrete Wavelet Packet Transform","authors":"Mouhamad Chehaitly, M. Tabaa, F. Monteiro, A. Dandache","doi":"10.1109/DCIS.2015.7388599","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388599","url":null,"abstract":"Discrete Wavelet Packet Transformation (DWPT) has been gaining much popularity in recent communication systems as a core transmission function, both as signal analysis or denoising technique. This trend is largely due to the mathematical properties of DWPT, and particularly to its excellent locality in the time-frequency domain. Unfortunately, DWPT is also a rather demanding operation. For instance, the much known tree algorithm developed by Mallat requires large amounts of operative and storage resources. In this paper, we are proposing a novel architecture for DWPT, aiming to provide an effective performance trade-off. High throughput is achieved using only a relatively limited amount of hardware, thanks to a clever sharing of hardware resources between the low-pass and high-pass filters in the Mallat-tree algorithm, and an efficient use of the different throughput rates in different places of the architecture. The design has been modeled in VHDL at the RTL level, and synthesized using Altera Quartus II targeting an Altera Cyclone IV FPGA. The architecture is fully configurable at synthesis according to the tree depth (number of tree levels), the order of the filters and the filter coefficient quantization. Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. The results obtained so far compare favorably to previous works.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129734051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

An amplifier and capacitor sharing technique using recycling folded cascode operational amplifier with applications in MDAC of CMOS pipelined ADC 一种利用循环折叠级联运算放大器的放大器和电容共享技术，应用于CMOS流水线ADC的MDAC

2015 Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 1900-01-01 DOI: 10.1109/DCIS.2015.7388613

Denis Rogerio da Silva, N. Oki

引用次数: 2