{"title":"一种利用循环折叠级联运算放大器的放大器和电容共享技术,应用于CMOS流水线ADC的MDAC","authors":"Denis Rogerio da Silva, N. Oki","doi":"10.1109/DCIS.2015.7388613","DOIUrl":null,"url":null,"abstract":"An amplifier and capacitor sharing technique with applications in a multiplying digital-to-analog converter (MDAC) of CMOS pipelined ACDC is presented. The amplifier used in this implementation is a recycling amplifier based on the folded cascode operational amplifier with gain improved using positive feedback. The operational amplifier designed in 0.35um CMOS process show a simulated gain of 75 dB, frequency bandwidth of 95 MHz, phase margin of 75 degree and power consumption of 0.75 mW on a 1.8V power supply. The simulation results in MDAC of 1.5 bits show that this configuration can be used in a implementation of a 10 bits 10 MSample/s CMOS pipelined ADC with 2.8 mW power consumption (analog part) on a 1.8V supply.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An amplifier and capacitor sharing technique using recycling folded cascode operational amplifier with applications in MDAC of CMOS pipelined ADC\",\"authors\":\"Denis Rogerio da Silva, N. Oki\",\"doi\":\"10.1109/DCIS.2015.7388613\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An amplifier and capacitor sharing technique with applications in a multiplying digital-to-analog converter (MDAC) of CMOS pipelined ACDC is presented. The amplifier used in this implementation is a recycling amplifier based on the folded cascode operational amplifier with gain improved using positive feedback. The operational amplifier designed in 0.35um CMOS process show a simulated gain of 75 dB, frequency bandwidth of 95 MHz, phase margin of 75 degree and power consumption of 0.75 mW on a 1.8V power supply. The simulation results in MDAC of 1.5 bits show that this configuration can be used in a implementation of a 10 bits 10 MSample/s CMOS pipelined ADC with 2.8 mW power consumption (analog part) on a 1.8V supply.\",\"PeriodicalId\":191482,\"journal\":{\"name\":\"2015 Conference on Design of Circuits and Integrated Systems (DCIS)\",\"volume\":\"134 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Conference on Design of Circuits and Integrated Systems (DCIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCIS.2015.7388613\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS.2015.7388613","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An amplifier and capacitor sharing technique using recycling folded cascode operational amplifier with applications in MDAC of CMOS pipelined ADC
An amplifier and capacitor sharing technique with applications in a multiplying digital-to-analog converter (MDAC) of CMOS pipelined ACDC is presented. The amplifier used in this implementation is a recycling amplifier based on the folded cascode operational amplifier with gain improved using positive feedback. The operational amplifier designed in 0.35um CMOS process show a simulated gain of 75 dB, frequency bandwidth of 95 MHz, phase margin of 75 degree and power consumption of 0.75 mW on a 1.8V power supply. The simulation results in MDAC of 1.5 bits show that this configuration can be used in a implementation of a 10 bits 10 MSample/s CMOS pipelined ADC with 2.8 mW power consumption (analog part) on a 1.8V supply.