一种利用循环折叠级联运算放大器的放大器和电容共享技术,应用于CMOS流水线ADC的MDAC

Denis Rogerio da Silva, N. Oki
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引用次数: 2

摘要

提出了一种放大器和电容共享技术,并应用于CMOS流水线ACDC的倍增数模转换器(MDAC)。在这个实现中使用的放大器是一个基于折叠级联码运算放大器的循环放大器,使用正反馈来提高增益。采用0.35um CMOS工艺设计的运算放大器在1.8V电源下的模拟增益为75 dB,带宽为95 MHz,相位裕度为75度,功耗为0.75 mW。在1.5位MDAC中的仿真结果表明,该配置可用于在1.8V电源下实现功耗为2.8 mW(模拟部分)的10位10 MSample/s CMOS流水线ADC。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An amplifier and capacitor sharing technique using recycling folded cascode operational amplifier with applications in MDAC of CMOS pipelined ADC
An amplifier and capacitor sharing technique with applications in a multiplying digital-to-analog converter (MDAC) of CMOS pipelined ACDC is presented. The amplifier used in this implementation is a recycling amplifier based on the folded cascode operational amplifier with gain improved using positive feedback. The operational amplifier designed in 0.35um CMOS process show a simulated gain of 75 dB, frequency bandwidth of 95 MHz, phase margin of 75 degree and power consumption of 0.75 mW on a 1.8V power supply. The simulation results in MDAC of 1.5 bits show that this configuration can be used in a implementation of a 10 bits 10 MSample/s CMOS pipelined ADC with 2.8 mW power consumption (analog part) on a 1.8V supply.
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