Digital pseudorandom uniform noise generators for ADC histogram test

Abstract

This paper presents the evaluation of two different digital pseudorandom uniform noise generators (UNGs) applied to ADC histogram test. Two 32 bits pseudorandom uniform noise generators, a Mersenne-Twister (MTW) and a Linear Feedback Shift Register (LFSR), were implemented on a FPGA and evaluated to prove its validity in a proposed ADC built-in self-test (BIST) [1,2]. The BIST solution is based in the histogram method and the obtained results were compared with the ADC standard static test and with a histogram test using Gaussian noise as stimulus. A pipeline ADC and a DAC, both with a resolution of 10 bits, the Gaussian noise generator and the BIST solution were modeled and simulated in MATLAB. The obtained results shown that the histogram test with an UNG as a stimulus could be a powerful method to characterize 10 bits ADCs with the accuracy needed. Compared with the Gaussian histogram test, the number and complexity of the circuits is quite reduced and an adequate statistical significance is obtained with a quarter of samples, therefore the time required for tests is reduced.