Embedding Fault List Compression techniques in a design automation framework for analog and Mixed-Signal structural testing

Abstract

The innovative work “Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression” [1] focuses on the prohibitive number of structural faults which need to be simulated, at circuit-level, in the design environment. It proposes a fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. The methodology allows different tradeoffs between fault list compression and fault representation accuracy by changing the number of strata, L. These concepts are embed them in the AIDA's framework [2][3], which is an analog IC design automation environment, and, allows the designer to select a circuit sizing and determine an efficient set of stimuli for fault detection, reducing the simulations required in the test environment. A single ended 2-stage amplifier is used here to demonstrate the proposed developments in the field of structural testing. All the results are presented for the United Microelectronics Corporation (UMC) 130 nanometers technology node.