A fast and configurable architecture for Discrete Wavelet Packet Transform

Abstract

Discrete Wavelet Packet Transformation (DWPT) has been gaining much popularity in recent communication systems as a core transmission function, both as signal analysis or denoising technique. This trend is largely due to the mathematical properties of DWPT, and particularly to its excellent locality in the time-frequency domain. Unfortunately, DWPT is also a rather demanding operation. For instance, the much known tree algorithm developed by Mallat requires large amounts of operative and storage resources. In this paper, we are proposing a novel architecture for DWPT, aiming to provide an effective performance trade-off. High throughput is achieved using only a relatively limited amount of hardware, thanks to a clever sharing of hardware resources between the low-pass and high-pass filters in the Mallat-tree algorithm, and an efficient use of the different throughput rates in different places of the architecture. The design has been modeled in VHDL at the RTL level, and synthesized using Altera Quartus II targeting an Altera Cyclone IV FPGA. The architecture is fully configurable at synthesis according to the tree depth (number of tree levels), the order of the filters and the filter coefficient quantization. Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. The results obtained so far compare favorably to previous works.