2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)最新文献_第3页

Threshold voltage defined multi-input complex gates 阈值电压定义多输入复合门

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951828

Asmit De, Swaroop Ghosh

{"title":"Threshold voltage defined multi-input complex gates","authors":"Asmit De, Swaroop Ghosh","doi":"10.1109/HST.2017.7951828","DOIUrl":"https://doi.org/10.1109/HST.2017.7951828","url":null,"abstract":"Semiconductor devices are increasingly getting more vulnerable to counterfeiting due to Reverse Engineering (RE) of Intellectual Property (IP). Securing the IPs from counterfeiting is an important goal towards trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an adversary from de-layering the chip and stealing IP. Among other techniques, threshold voltage modulation has been proposed to realize 2-input camouflaging logic in both static and dynamic logic gate families. Since threshold voltages are asserted during fabrication and are difficult to identify during reverse engineering, the adversary will be forced to launch brute-force search. In this work, we extend the concept of threshold-voltage defined logic to design 3-input static camouflaged gates capable of performing six Boolean functions (NAND, NOR, AOI, OAI, XOR, XNOR). Simulation results show an average of 3.03X delay overhead and 12.33X power overhead compared to standard CMOS gates. The area benefit with respect to cumulative sum of 6 discreet normal CMOS gates is approximately 65%. A methodology to design multi-input camouflaged gate is also proposed using a similar technique. We also identify temperature sensitivity and power signature as potential side channels. Finally, a threat analysis is performed on the camouflaged gate design to assess the security and integrity of the design.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122380293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Stateless leakage resiliency from NLFSRs nlfsr的无状态泄漏弹性

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951798

Mostafa M. I. Taha, A. Reyhani-Masoleh, P. Schaumont

{"title":"Stateless leakage resiliency from NLFSRs","authors":"Mostafa M. I. Taha, A. Reyhani-Masoleh, P. Schaumont","doi":"10.1109/HST.2017.7951798","DOIUrl":"https://doi.org/10.1109/HST.2017.7951798","url":null,"abstract":"Stateless cryptographic functions are required whenever the two communicating parties are not synchronized (have no memory of previous connection). It is widely accepted that these functions can only be efficiently secured against Side-Channel Analysis (SCA) using the regular countermeasures (masking and hiding). On the other hand, leakage resiliency tries to design new cryptographic functions with inherent security against SCA attacks. Generally, there are two methods to design stateless leakage resilient functions: tree structures and key-dependent algorithmic noise. Unfortunately, the first method is computationally intensive, while the current designs under the second method offer low security guarantees. In this paper, we follow the second approach to design a stateless leakage resilient function using non-linear feedback shift registers (NLFSRs). Our results show that the uncertainty on an n-bit key after any SCA attack exceeds n/2 bits, the birthday boundary, and can approach n bits, the brute-force boundary. We validate security of our structure with mathematical models and Monte Carlo simulation at noise-free conditions.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122096413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF 一种改善硬件嵌入式延迟PUF位串质量的新偏移方法

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951821

Wenjie Che, J. Plusquellic, F. Saqib

引用次数: 0

Hermes: Secure heterogeneous multicore architecture design Hermes:安全的异构多核架构设计

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951731

M. Kinsy, Shreeya Khadka, Mihailo Isakov, Anam Farrukh

{"title":"Hermes: Secure heterogeneous multicore architecture design","authors":"M. Kinsy, Shreeya Khadka, Mihailo Isakov, Anam Farrukh","doi":"10.1109/HST.2017.7951731","DOIUrl":"https://doi.org/10.1109/HST.2017.7951731","url":null,"abstract":"The emergence of general-purpose system-on-chip (SoC) architectures has given rise to a number of significant security challenges. The current trend in SoC design is system-level integration of heterogeneous technologies consisting of a large number of processing elements such as programmable RISC cores, memory, DSPs, and accelerator function units/ASIC. These processing elements may come from different providers, and application executable code may have varying levels of trust. Some of the pressing architecture design questions are: (1) how to implement multi-level user-defined security; (2) how to optimally and securely share resources and data among processing elements. In this work, we develop a secure multicore architecture, named Hermes. It represents a new architectural framework that integrates multiple processing elements (called tenants) of secure and non-secure cores into the same chip design while (a) maintaining individual tenant security, (b) preventing data leakage and corruption, and (c) promoting collaboration among the tenants. The Hermes architecture is based on a programmable secure router interface and a trust-aware routing algorithm. With 17% hardware overhead, it enables the implementation of processing-element-oblivious secure multicore systems with a programmable distributed group key management scheme.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134410736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Using computational game theory to guide verification and security in hardware designs 利用计算博弈论指导硬件设计中的验证和安全

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951808

Andrew M. Smith, J. Mayo, V. Kammler, R. Armstrong, Yevgeniy Vorobeychik

{"title":"Using computational game theory to guide verification and security in hardware designs","authors":"Andrew M. Smith, J. Mayo, V. Kammler, R. Armstrong, Yevgeniy Vorobeychik","doi":"10.1109/HST.2017.7951808","DOIUrl":"https://doi.org/10.1109/HST.2017.7951808","url":null,"abstract":"Verifying that hardware design implementations adhere to specifications is a time intensive and sometimes intractable problem due to the massive size of the system's state space. Formal methods techniques can be used to prove certain tractable specification properties; however, they are expensive, and often require subject matter experts to develop and solve. Nonetheless, hardware verification is a critical process to ensure security and safety properties are met, and encapsulates problems associated with trust and reliability. For complex designs where coverage of the entire state space is unattainable, prioritizing regions most vulnerable to security or reliability threats would allow efficient allocation of valuable verification resources. Stackelberg security games model interactions between a defender, whose goal is to assign resources to protect a set of targets, and an attacker, who aims to inflict maximum damage on the targets after first observing the defender's strategy. In equilibrium, the defender has an optimal security deployment strategy, given the attacker's best response. We apply this Stackelberg security framework to synthesized hardware implementations using the design's network structure and logic to inform defender valuations and verification costs. The defender's strategy in equilibrium is thus interpreted as a prioritization of the allocation of verification resources in the presence of an adversary. We demonstrate this technique on several open-source synthesized hardware designs.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124556143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Reviving instruction set randomization 恢复指令集随机化

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951732

Kanad Sinha, V. Kemerlis, S. Sethumadhavan

引用次数: 29

LWE-based lossless computational fuzzy extractor for the Internet of Things 基于lwe的物联网无损计算模糊提取器

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951818

Christopher Huth, Daniela Becker, J. Guajardo, P. Duplys, T. Güneysu

{"title":"LWE-based lossless computational fuzzy extractor for the Internet of Things","authors":"Christopher Huth, Daniela Becker, J. Guajardo, P. Duplys, T. Güneysu","doi":"10.1109/HST.2017.7951818","DOIUrl":"https://doi.org/10.1109/HST.2017.7951818","url":null,"abstract":"With the advent of the Internet of Things, lightweight devices necessitate secure and cost-efficient key storage. Since traditional secure key storage is expensive, novel solutions have been developed based on the idea of deriving the key from noisy entropy sources. Such sources when combined with fuzzy extractors allow cryptographically strong key derivation. Information theoretic fuzzy extractors require large amounts of input entropy to account for entropy loss in the key extraction process. It has been shown by Fuller et al. (ASIACRYPT'13) that the entropy loss can be reduced if the security requirement is relaxed to computational security based on the hardness of the Learning with Errors problem. We present the first implementation of a lossless computational fuzzy extractor (CFE) where the entropy of the source equals the entropy of the key. We explore efficiency and complexity design trade-offs for a system based on the implementation of a lossless CFE on a constrained device. To investigate the limits of the construction, we choose as implementation platforms a very constrained 8-bit AVR microcontroller device, as well as a 32-bit ARM Cortex-M3 microcontroller device. The latter speeds up the clients generate procedure from 34.9 to 0.4 seconds. We also show how to reduce the memory footprint of the algorithms proposed by Fuller et al. Our implementation requires only 1.45KB of SRAM and 9.8KB of Flash memory on an 8-bit microcontroller. Our evaluation indicates that it is feasible to implement such CFE schemes in highly constrained environments.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117302934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Parameter biasing obfuscation for analog IP protection 模拟IP保护的参数偏置混淆

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951825

Vaibhav Venugopal Rao, I. Savidis

{"title":"Parameter biasing obfuscation for analog IP protection","authors":"Vaibhav Venugopal Rao, I. Savidis","doi":"10.1109/HST.2017.7951825","DOIUrl":"https://doi.org/10.1109/HST.2017.7951825","url":null,"abstract":"A unique key-based technique that obfuscates the critical biasing conditions of an analog circuit is developed. The proposed technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The width of a transistor is obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied, certain transistor(s) are active, and the correct biasing points are set at the target node. The proposed bias encryption technique is implemented on a VCO based phase locked loop (PLL) in a standard 180nm CMOS process. Circuit parameters including the settling time, power, and phase noise for both the obfuscated and an un-obfuscated PLL are compared. A 40-bit encryption key is used to obfuscate biasing parameters, significantly improving the security of an analog IC. Obfuscating the PLL results in a 6.3% increase in area, 0.89% increase in power consumption, and 5 dBc/Hz increase in phase noise. The probability to determine the correct key through brute force attack is 9.095×10−13. By implementing the proposed technique on multiple analog components in the integrated circuit, the key space is increased and the overall security is further improved. The analog obfuscation technique complements existing digital encryption techniques and is an effective countermeasure against IP theft, counterfeiting, and overproduction of analog and mixed signal circuits.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123841792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Correlation power analysis attack against STT-MRAM based cyptosystems 基于STT-MRAM的细胞系统相关功率分析攻击

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951835

Abhishek Chakraborty, Ankit Mondal, Ankur Srivastava

{"title":"Correlation power analysis attack against STT-MRAM based cyptosystems","authors":"Abhishek Chakraborty, Ankit Mondal, Ankur Srivastava","doi":"10.1109/HST.2017.7951835","DOIUrl":"https://doi.org/10.1109/HST.2017.7951835","url":null,"abstract":"Emerging technologies such as Spin-transfer torque magnetic random-access memory (STT-MRAM) are considered potential candidates for implementing low-power, high density storage systems. The vulnerability of such nonvolatile memory (NVM) based cryptosystems to standard side-channel attacks must be thoroughly assessed before deploying them in practice. In this paper, we outline a generic Correlation Power Analysis (CPA) attack strategy against STT-MRAM based cryptographic designs using a new power model. In our proposed attack methodology, an adversary exploits the power consumption patterns during the write operation of an STT-MRAM based cryptographic implementation to successfully retrieve the secret key. In order to validate our proposed attack technique, we mounted a CPA attack on MICKEY-128 2.0 stream cipher design consisting of STT-MRAM cells with Magnetic Tunnel Junctions (MTJs) as storage elements. The results of the experiments show that the STT-MRAM based implementation of the cipher circuit is susceptible to standard differential power analysis attack strategy provided a suitable hypothetical power model (such as the one proposed in this paper) is selected. In addition, we also investigated the effectiveness of state-of-the-art side-channel attack countermeasures for MRAMs and found that our proposed scheme is able to break such protected implementations as well.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Photonic side channel attacks against RSA 针对RSA的光子侧信道攻击

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951801

Elad Carmon, Jean-Pierre Seifert, A. Wool

引用次数: 19