Threshold voltage defined multi-input complex gates

Semiconductor devices are increasingly getting more vulnerable to counterfeiting due to Reverse Engineering (RE) of Intellectual Property (IP). Securing the IPs from counterfeiting is an important goal towards trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an adversary from de-layering the chip and stealing IP. Among other techniques, threshold voltage modulation has been proposed to realize 2-input camouflaging logic in both static and dynamic logic gate families. Since threshold voltages are asserted during fabrication and are difficult to identify during reverse engineering, the adversary will be forced to launch brute-force search. In this work, we extend the concept of threshold-voltage defined logic to design 3-input static camouflaged gates capable of performing six Boolean functions (NAND, NOR, AOI, OAI, XOR, XNOR). Simulation results show an average of 3.03X delay overhead and 12.33X power overhead compared to standard CMOS gates. The area benefit with respect to cumulative sum of 6 discreet normal CMOS gates is approximately 65%. A methodology to design multi-input camouflaged gate is also proposed using a similar technique. We also identify temperature sensitivity and power signature as potential side channels. Finally, a threat analysis is performed on the camouflaged gate design to assess the security and integrity of the design.