Parameter biasing obfuscation for analog IP protection

Abstract

A unique key-based technique that obfuscates the critical biasing conditions of an analog circuit is developed. The proposed technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The width of a transistor is obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied, certain transistor(s) are active, and the correct biasing points are set at the target node. The proposed bias encryption technique is implemented on a VCO based phase locked loop (PLL) in a standard 180nm CMOS process. Circuit parameters including the settling time, power, and phase noise for both the obfuscated and an un-obfuscated PLL are compared. A 40-bit encryption key is used to obfuscate biasing parameters, significantly improving the security of an analog IC. Obfuscating the PLL results in a 6.3% increase in area, 0.89% increase in power consumption, and 5 dBc/Hz increase in phase noise. The probability to determine the correct key through brute force attack is 9.095×10−13. By implementing the proposed technique on multiple analog components in the integrated circuit, the key space is increased and the overall security is further improved. The analog obfuscation technique complements existing digital encryption techniques and is an effective countermeasure against IP theft, counterfeiting, and overproduction of analog and mixed signal circuits.