2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)最新文献_第4页

Challenging on-chip SRAM security with boot-state statistics 用引导状态统计挑战片上SRAM安全性

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951806

Joseph McMahan, Weilong Cui, Liangzhao Xia, Jeff Heckey, F. Chong, T. Sherwood

引用次数: 3

Ag conductive bridge RAMs for physical unclonable functions 用于物理不可克隆功能的银导电桥ram

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951815

B. Cambou, F. Afghah, D. Sonderegger, J. Taggart, H. Barnaby, M. Kozicki

{"title":"Ag conductive bridge RAMs for physical unclonable functions","authors":"B. Cambou, F. Afghah, D. Sonderegger, J. Taggart, H. Barnaby, M. Kozicki","doi":"10.1109/HST.2017.7951815","DOIUrl":"https://doi.org/10.1109/HST.2017.7951815","url":null,"abstract":"We are presenting a method to design reliable physical unclonable functions (PUFs), with silver based conductive-bridge random access memory (CB-RAM) arrays, to protect the internet of things (loT). The arrays that we fabricated in our pilot line, and characterized, operate at extremely low power which is highly desirable for security applications, and to protect cryptographic primitives. The experimental data presented in this work supports the selection of the programming voltage, the Vset, as the parameter, to generate PUF challenge-response pairs (CRP). The median Vset voltage at 0.12V is orders of magnitude lower than other non-volatile memory technologies, which can reduce the threat of side channel analysis. The level of stability, cell to cell, of the Vset that we characterized is acceptable when combined with methods based on ternary states, and resulted in low CRP error rates. Built-in-self-test capability (BIST) is used to differentiate unstable cells of the array, that carry the state “X”, from the solid cells carrying the states “0” and “1”, which are capable of generating reliable PUF CRPs. The use of machine learning algorithms can also compensate for the temperature drifts, noise, aging, and measurement instabilities normal variations. This research work is currently used to finalize and design a prototype with a custom state machine, and FPGA. We will fabricate various CB-RAM samples to optimize the quality of the PUFs.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116898015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

A novel physiological features-assisted architecture for rapidly distinguishing health problems from hardware Trojan attacks and errors in medical devices 一种新的生理特征辅助架构，用于快速区分医疗设备中的健康问题与硬件木马攻击和错误

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951807

Taimour Wehbe, V. Mooney, A. Q. Javaid, O. Inan

引用次数: 15

On secure implementations of quantum-resistant supersingular isogeny Diffie-Hellman 抗量子超奇异等源Diffie-Hellman的安全实现

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951824

Brian Koziel, R. Azarderakhsh, David Jao

{"title":"On secure implementations of quantum-resistant supersingular isogeny Diffie-Hellman","authors":"Brian Koziel, R. Azarderakhsh, David Jao","doi":"10.1109/HST.2017.7951824","DOIUrl":"https://doi.org/10.1109/HST.2017.7951824","url":null,"abstract":"In this work, we analyze the feasibility of a physically secure implementation of the quantum-resistant supersingular isogeny Diffie-Hellman (SIDH) protocol. Notably, we analyze the defense against timing attacks, simple power analysis, differential power analysis, and fault attacks. Luckily, the SIDH protocol closely resembles its predecessor, the elliptic curve Diffie-Hellman (ECDH) key exchange. As such, much of the extensive literature in side-channel analysis can also apply to SIDH. In particular, we focus on a hardware implementation that features a true random number generator, ALU, and controller. SIDH is composed of two rounds containing a double-point multiplication to generate a secret kernel point and an isogeny over that kernel to arrive at a new elliptic curve isomorphism. To protect against simple power analysis and timing attacks, we recommend a constant-time implementation with Fermat's little theorem inversion. Differential power analysis targets the power output of the SIDH core over many runs. As such, we recommend scaling the base points by secret scalars so that each iteration has a unique power signature. Further, based on recent oracle attacks on SIDH, we cannot recommend the use of static keys from both parties. The goal of this paper is to analyze the tradeoffs in elliptic curve theory to produce a cryptographically and physically secure implementation of SIDH.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126606369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Memory-constrained implementation of lattice-based encryption scheme on standard Java Card 基于格子的加密方案在标准Java卡上的内存约束实现

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951796

Ye Yuan, Kazuhide Fukushima, S. Kiyomoto, T. Takagi

{"title":"Memory-constrained implementation of lattice-based encryption scheme on standard Java Card","authors":"Ye Yuan, Kazuhide Fukushima, S. Kiyomoto, T. Takagi","doi":"10.1109/HST.2017.7951796","DOIUrl":"https://doi.org/10.1109/HST.2017.7951796","url":null,"abstract":"Since NSA announced the plans for transitioning to the algorithms which are resistant to attacks by the potential quantum computers, the interest of implementation of post-quantum cryptography (PQC) on various devices has emerged. Including widely used Java Card, memory-constrained smart cards need the efficient implementation of encryption schemes to resist quantum-computing attacks. Meanwhile, lattice-based cryptography, as one of the strongest candidates for PQC, has attracted wide attention due to their applicability and operating efficiency in recent years. However, due to the limited memory resources and computing power, long integer multiplication is a challenge on Java Card, and it had been considered that only a few lattice-based cryptosystems are fitting into such devices. In this paper, we show the first implementation of a lattice-based encryption scheme on standard Java Card whose running time is nearly optimal (about 100 seconds in decryption for 128-bit security) by combining the use of iterative fast Fourier transform and improved Montgomery modular multiplication. More importantly, we indicate that polynomial multiplication and over signed 15-bit integer arithmetic can be performed on Java Card even if the long integers are not supported, which makes running more lattice-based protocols on Java Card achievable.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126311882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Abstract: Characterizing EEPROM for usage as a ubiquitous PUF source 摘要:描述EEPROM作为一种普遍存在的PUF源的特性

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951832

Chris Pavlina, Jacob I. Torrey, Kyle J. Temkin

{"title":"Abstract: Characterizing EEPROM for usage as a ubiquitous PUF source","authors":"Chris Pavlina, Jacob I. Torrey, Kyle J. Temkin","doi":"10.1109/HST.2017.7951832","DOIUrl":"https://doi.org/10.1109/HST.2017.7951832","url":null,"abstract":"Physical Unclonable Functions (PUFs) are increasingly being employed as a security primitive in hardware devices. PUFs are used to both empower authentication of individual hardware devices and support derivation of hardware-specific keys. By exposing the process variation in silicon devices as a source of the unpredictable but repeatable unique response to a challenge, PUFs can provide features that typically need dedicated security hardware (e.g., TPMs). A novel PUF source based on the write timing of Electrically Eraseable Programmable ROMs (EEPROMs) is demonstrated in certain process ICs. EEPROM cells are programmed via a process which gradually accrues charge carriers within the gate of a memory cell. Many EEPROMs require relatively long write cycles to establish stable memory contents. If a write operation is not sustained for the requisite duration, the resulting value stored in memory is dependent on physical properties heavily impacted by process variation. As EEPROMs are found on every PC DRAM module and exposed to software via a standardized I2C bus, this PUF source has potential to be both ubiquitous and software-accessible without any modifications to the off-the-shelf hardware. A set of EEPROMs have been tested for suitability for this PUF. Arrays of 64 of each of six device types were constructed and tested for bits of usable entropy, HDinter, and HDintra. The EEPROMs with coarse feature size produced around 90% usable entropy relative to memory size, with HDintra mostly around 45–55% and HDintra mostly under 7%.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123147062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Synthesis of hardware sandboxes for Trojan mitigation in systems on chip 在芯片系统中合成硬件沙盒以缓解木马威胁

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951836

C. Bobda, Taylor J. L. Whitaker, C. Kamhoua, K. Kwiat, L. Njilla

{"title":"Synthesis of hardware sandboxes for Trojan mitigation in systems on chip","authors":"C. Bobda, Taylor J. L. Whitaker, C. Kamhoua, K. Kwiat, L. Njilla","doi":"10.1109/HST.2017.7951836","DOIUrl":"https://doi.org/10.1109/HST.2017.7951836","url":null,"abstract":"In this work, we propose a design flow for automatic generation of hardware sandboxes purposed for IP security in trusted system-on-chips (SoCs). Our tool CAPSL, the Component Authentication Process for Sandboxed Layouts, is capable of detecting trojan activation and nullifying possible damage to a system at run-time, avoiding complex pre-fabrication and pre-deployment testing for trojans. Our approach captures the behavioral properties of non-trusted IPs, typically from a third-party or components off the shelf (COTS), with the formalism of interface automata and the Property Specification Language's sequential extended regular expressions (SERE). Using the concept of hardware sandboxing, we translate the property specifications to checker automata and partition an untrusted sector of the system, with included virtualized resources and controllers, to isolate sandbox-system interactions upon deviation from the behavioral checkers. Our design flow is verified with benchmarks from Trust-Hub.org, which show 100% trojan detection with reduced checker overhead compared to other run-time verification techniques.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126833117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems 资源受限嵌入式系统安全的物理不可克隆功能和动态局部重构

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951809

Goutham Pocklassery, Venkata K. Kajuruli, J. Plusquellic, F. Saqib

{"title":"Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems","authors":"Goutham Pocklassery, Venkata K. Kajuruli, J. Plusquellic, F. Saqib","doi":"10.1109/HST.2017.7951809","DOIUrl":"https://doi.org/10.1109/HST.2017.7951809","url":null,"abstract":"Authentication and encryption within an embedded system environment using cameras, sensors, thermostats, autonomous vehicles, medical implants, RFID, etc. is becoming increasing important with ubiquitious wireless connectivity. Hardware-based authentication and encryption offer several advantages in these types of resource-constrained applications, including smaller footprints and lower energy consumption. Bitstring and key generation implemented with Physical Unclonable Functions or PUFs can further reduce resource utilization for authentication and encryption operations and reduce overall system cost by eliminating on-chip non-volatile-memory (NVM). In this paper, we propose a dynamic partial reconfiguration (DPR) strategy for implementing both authentication and encryption using a PUF for bitstring and key generation on FPGAs as a means of optimizing the utilization of the limited area resources. We show that the time and energy penalties associated with DPR are small in modern SoC-based architectures, such as the Xilinx Zynq SoC, and therefore, the overall approach is very attractive for emerging resource-constrained IoT applications.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Towards a memristive hardware secure hash function (MemHash) 一种记忆硬件安全哈希函数(MemHash)

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951797

Leonid Azriel, Shahar Kvatinsky

{"title":"Towards a memristive hardware secure hash function (MemHash)","authors":"Leonid Azriel, Shahar Kvatinsky","doi":"10.1109/HST.2017.7951797","DOIUrl":"https://doi.org/10.1109/HST.2017.7951797","url":null,"abstract":"Hardware based hash functions might provide a low cost and low power alternative to the classic solutions, which are based on implementations of mathematical cryptographic algorithms. In this paper, we propose MemHash, a hardware secure hash function built using memristive technology that exploits the unique properties of memristors. The MemHash operation is based on intrinsic device characteristics. Furthermore, it exploits process variations for implicit key embedding, thus creating a keyed-hash message authentication code (HMAC) that does not involve a separate key generation and management process. MemHash comprises a memristive crossbar with a differential read mechanism and a scrambler unit. The scrambler unit receives the input message as a bit stream and digitally mixes it with data read from the array. For every bit of the message, the scrambler generates a write address and a value to perform a single-cell write cycle to the crossbar. Because the crossbar is designed to be extremely sensitive to the write disturb phenomenon, every single-cell write alters additional cells in the design, thus increasing the entropy. The differential read mechanism provides sensitivity to process variations and robustness in operating conditions, yielding a PUF-like effect. MemHash is evaluated with a 16 × 16 memristive crossbar structure. Our simulation results demonstrate the statistical characteristics of the proposed design, showing close-to-optimal uniqueness and diffuseness.","PeriodicalId":190635,"journal":{"name":"2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134367349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

TTLock: Tenacious and traceless logic locking TTLock:持久的、无跟踪的逻辑锁定

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2017-05-01 DOI: 10.1109/HST.2017.7951830

Muhammad Yasin, Bodhisatwa Mazumdar, J. Rajendran, O. Sinanoglu

引用次数: 22