发布求助
文献互助 智能选刊 最新文献

IEEE International SOC Conference, 2004. Proceedings.最新文献

筛选
英文 中文
A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip 一个0.13/spl mu/m / 1Gb/s/通道的片上存储转发网络
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362381
F. Mondinelli, M. Borgatti, Z. Kovács-Vajna
{"title":"A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip","authors":"F. Mondinelli, M. Borgatti, Z. Kovács-Vajna","doi":"10.1109/SOCC.2004.1362381","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362381","url":null,"abstract":"A parametric packed-switched scalable network on chip allows energy/throughput/latency tradeoff for data-intensive communication-centric systems. At a clock rate of 200MHz the network guarantees block-free average 1 Gb/s per channel. The test chip includes 64-interfaces network on chip and traffic generators.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correction 一种包含非线性运算放大器增益和参考误差校正的流水线adc背景校正方案
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362343
A. Larsson, S. Sonkusale
{"title":"A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correction","authors":"A. Larsson, S. Sonkusale","doi":"10.1109/SOCC.2004.1362343","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362343","url":null,"abstract":"This paper presents a background noninvasive true calibration technique to correct for nonidealities in pipelined analog-to-digital converters (ADCs). Pipelined ADC suffers from finite nonlinear gain in amplifiers, ratio mismatch in capacitors, and errors in voltage references. Most calibration schemes do not account for reference voltage errors or nonlinearity in amplifiers, which introduce severe distortion in pipelined ADCs designed in a deep-submicron and nanometer-scale digital CMOS process. The proposed digital calibration scheme uses an insignificant, low-speed, low-power, high-resolution sigma-delta ADC to estimate a set of digital error-correction parameters in background using an adaptive LMS algorithm. The technique is shown to correct all static errors within a single framework - finite amplifier gain, capacitor ratio mismatch, voltage reference errors and amplifier nonlinearity. The scheme is demonstrated for a 14-bit A/D converter intended for speeds higher than 100Msample/s.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123996568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low energy transmission coding for on-chip serial communications 片上串行通信的低能量传输编码
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362398
Kangmin Lee, Se-Joong Lee, H. Yoo
{"title":"Low energy transmission coding for on-chip serial communications","authors":"Kangmin Lee, Se-Joong Lee, H. Yoo","doi":"10.1109/SOCC.2004.1362398","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362398","url":null,"abstract":"A coding method to reduce the transmission energy of a serial communication by minimizing the number of transitions on the serial wire is proposed. We apply the coding technique to a CMOS SoC, which integrates various processing units with packet switched on-chip networks. With a multimedia application running, the power reduction on serial wires is up to 49%.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130441071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An embedded read only memory architecture with a complementary and two interchangeable power/performance design points 具有互补和两个可互换的功率/性能设计点的嵌入式只读存储器架构
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362403
S. Eustis
{"title":"An embedded read only memory architecture with a complementary and two interchangeable power/performance design points","authors":"S. Eustis","doi":"10.1109/SOCC.2004.1362403","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362403","url":null,"abstract":"This paper focuses on the features of a 0.13 /spl mu/m embedded, compilable read only memory (ROM). A complementary array cell is described which increases and maintains signal margins across array sizes despite the ever-increasing capacitive coupling effects and lower voltages of each succeeding technology generation. A new architecture is described which allows a customer to switch between two different power/performance design points while only changing the metal wiring in the ROM via a compiler. Hardware data is presented which illustrates the success of the array design and difference between the two power/performance design points.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulation 高效卡尔曼带通σ - δ滤波器的FPGA实现，用于调频解调
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362379
C. Charayaphan, S. Abeysekera
{"title":"FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulation","authors":"C. Charayaphan, S. Abeysekera","doi":"10.1109/SOCC.2004.1362379","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362379","url":null,"abstract":"An efficient architecture for Kalman band-pass sigma-delta (/spl Sigma/-/spl Delta/) demodulator, used in the application of FM demodulation, is presented. The IF stage of the circuit separates the inphase and quadrature (I and Q) signals using a single circuit path, thus eliminating I-Q differences due to component mismatch. The separated I-Q signals are then filtered using an efficient recursive Kalman band-pass filter. The demodulation performance of Kalman filter is evaluated. The FPGA (field programmable gate array) design of the architecture is given.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128747680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
SoC design of remote terminals for wireless telemetry system 无线遥测系统远程终端的SoC设计
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362462
Wonjae Lee, Sangyun Hwang, Minho Kwon, Seongjoo Lee, Jaeseok Kim
{"title":"SoC design of remote terminals for wireless telemetry system","authors":"Wonjae Lee, Sangyun Hwang, Minho Kwon, Seongjoo Lee, Jaeseok Kim","doi":"10.1109/SOCC.2004.1362462","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362462","url":null,"abstract":"In this paper, we present a SoC design of remote terminals for wireless telemetry system based on DS-CDMA technology. Wireless telemetry systems are data collecting system that gather the information data, such as temperature, pressure, humidity and etc, from lots of remote measurement points using wireless communication to the central unit. It can be used in ISM band having the severe interference because of the DS-CDMA technology and more than 1,000 remote terminals within 300m can be serviced at the same time. We designed the remote terminals as a SoC that is consisted of modem, digital IF, and analog circuit using a 0.25/spl mu/m single-poly five-metal CMOS process. The SoC implementation is essential for low cost and low power to satisfy the requirements of the wireless telemetry systems that need large amounts of remote terminals.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study 多滴，gb/s，存储总线的混合信号DFE -可行性研究
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362384
H. Fredriksson, C. Svensson
{"title":"Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study","authors":"H. Fredriksson, C. Svensson","doi":"10.1109/SOCC.2004.1362384","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362384","url":null,"abstract":"A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127186481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high-performance parallel mode EBCOT encoder architecture design for JPEG2000 基于JPEG2000的高性能并行模式EBCOT编码器架构设计
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362411
Yun Long, Chunhui Zhang, F. Kurdahi
{"title":"A high-performance parallel mode EBCOT encoder architecture design for JPEG2000","authors":"Yun Long, Chunhui Zhang, F. Kurdahi","doi":"10.1109/SOCC.2004.1362411","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362411","url":null,"abstract":"This paper proposes a new architecture for embedded block coding with optimized truncation (EBCOT) encoder in JPEG2000. As part of a JPEG2000 encoder embedded system under development, it is a parallel mode coder utilizing both code-block and bit-plane parallelisms. In low bit-rate lossy coding, the proposed architecture is roughly two times faster than the fastest existing EBCOT encoder in literature at similar hardware cost and also shows its advantages on memory efficiency, bandwidth requirement and scalability.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126055354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A power-aware scalable pipelined Booth multiplier 功率感知可扩展流水线布斯乘法器
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362373
Hanho Lee
{"title":"A power-aware scalable pipelined Booth multiplier","authors":"Hanho Lee","doi":"10.1109/SOCC.2004.1362373","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362373","url":null,"abstract":"Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this paper presents a low-power power-aware scalable pipelined Booth multiplier that makes use of the sharing common functional unit, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications. Our multiplier detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication operation. \"The multiplication mode is determined by the dynamic-range detection unit, which generates and dispatches the control signals for the pipeline stages. For the 8-bit and 4-bit computations, the proposed Booth multiplier leads to a 29% and 58% power consumption reduction over a non-scalable Booth multiplier, respectively. The proposed scalable pipelined Booth multiplier proves to be globally 20% more power efficient than a non-scalable pipelined Booth multiplier, and also it has fast speed due to pipelining.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121666134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 83
Power-efficient implementation of turbo decoder in SDR system SDR系统中turbo译码器的节能实现
IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362372
B. Kang, N. Vijaykrishnan, M. J. Irwin, T. Theocharides
{"title":"Power-efficient implementation of turbo decoder in SDR system","authors":"B. Kang, N. Vijaykrishnan, M. J. Irwin, T. Theocharides","doi":"10.1109/SOCC.2004.1362372","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362372","url":null,"abstract":"Turbo coding is widely used in wireless communication. Efficient implementation of turbo codes has significant impact on the power efficiency of mobile systems. Especially, as the need for software defined radio (SDR) system is growing, the appropriate selection of DSP processors becomes an important design issue. In this work, we show that using a processor that operates using the logarithmic number system is more power efficient for executing the turbo codes than traditional fixed point and floating point processors. Further, we modify the Logarithmic Number System (LNS) processor to support less accurate addition to reduce power consumed by max*, an important operation performed during turbo decoding. Our simulation shows that this optimization reduces the power consumption of turbo coding by 27.6% with negligible impact on the signal to noise ratio.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"54 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114019662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信