A power-aware scalable pipelined Booth multiplier

Abstract

Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery-powered wireless sensor network systems. Addressing this issue, this paper presents a low-power power-aware scalable pipelined Booth multiplier that makes use of the sharing common functional unit, ensemble of optimized Wallace-trees and a 4-bit array-based adder-tree for DSP applications. Our multiplier detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication operation. "The multiplication mode is determined by the dynamic-range detection unit, which generates and dispatches the control signals for the pipeline stages. For the 8-bit and 4-bit computations, the proposed Booth multiplier leads to a 29% and 58% power consumption reduction over a non-scalable Booth multiplier, respectively. The proposed scalable pipelined Booth multiplier proves to be globally 20% more power efficient than a non-scalable pipelined Booth multiplier, and also it has fast speed due to pipelining.