IEEE International SOC Conference, 2004. Proceedings.最新文献

A compensation technique for transistor mismatch in current mirrors 电流反射镜中晶体管失配的补偿技术

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362449

S. Bandi, P. R. Mukund

引用次数: 9

Mutual inductance modeling for multiple RLC interconnects with application to shield insertion 多RLC互连互感建模及其在屏蔽插入中的应用

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362457

Junmou Zhang, E. Friedman

引用次数: 7

Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1/spl trade/ standard [architecurtes read architectures] 利用蓝牙IEEE 802.15.1/spl贸易/标准通过领域特定可重构架构在短距离无线媒体上传输视频[架构读取架构]

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362331

Imran Ahmed, T. Arslan, S. Khawam

引用次数: 2

An asynchronous on-chip network router with quality-of-service (QoS) support 具有服务质量(QoS)支持的异步片上网络路由器

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362432

Tomaz Feliciian, S. Furber

引用次数: 93

A novel half-rate architecture for high-speed clock and data recovery 一种新颖的半速率架构，用于高速时钟和数据恢复

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362461

Qiurong He, M. Feng

引用次数: 0

High speed mixed analog/digital PRML architecture for optical data storage system 用于光学数据存储系统的高速混合模拟/数字PRML体系结构

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362410

M. Konakov, Jae-Wook Lee, Jung-Hyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee

引用次数: 0

Application specific instruction memory transformations for power efficient, fault resilient embedded processors 应用特定的指令存储器转换为节能，故障弹性嵌入式处理器

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362405

R. Ayoub, Peter Petrov, A. Orailoglu

{"title":"Application specific instruction memory transformations for power efficient, fault resilient embedded processors","authors":"R. Ayoub, Peter Petrov, A. Orailoglu","doi":"10.1109/SOCC.2004.1362405","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362405","url":null,"abstract":"In this paper we present a coding framework for a low energy instruction bus for embedded processors. The encoder exploits application-specific knowledge regarding program hot-spots to generate codewords that deliver savings in power and to furthermore provide concurrent detection of errors. Power savings can be obtained through the use of codewords that reduce the switching activity on the bus. The analysis shows that generating codewords that prohibit the occurrence of three consecutive transitions in three adjacent lines is fundamental to capturing the worst-case crosstalk faults in the bus lines at run time, thus improving the overall reliability of the bus. The desired codewords can be generated through a set of simple prespecified transformations. The detailed analysis we outline shows that the presented transformations are optimal. The proposed encoding scheme is dynamically reprogrammable, thus targeting code particularities effectively. The restriction to a simple yet efficient set of transformations reduces the required storage capacity and eases reprogrammability while achieving these objectives. Extensive experimental analysis on numerical and DSP codes indicates significant improvements in power savings.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134322457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analysis and design of monolithic, high PSR, linear regulators for SoC applications SoC应用的单片、高PSR线性稳压器的分析与设计

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362447

V. Gupta, G. Rincón-Mora, P. Raha

{"title":"Analysis and design of monolithic, high PSR, linear regulators for SoC applications","authors":"V. Gupta, G. Rincón-Mora, P. Raha","doi":"10.1109/SOCC.2004.1362447","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362447","url":null,"abstract":"Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply rejection (PSR) performance is magnified in SoC systems, given their inherently noisy environments. In this work, a simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived. The PSR of regulators that use PMOS output stages for low drop-out (LDO), crucial for modern low-voltage systems, is enhanced by error amplifiers which present a supply-correlated ripple at the gate of the PMOS pass device. On the other hand, amplifiers that suppress the supply ripple at their output are optimal for NMOS output stages since the source is now free from output ripple. A better PSR bandwidth, at the cost of dc PSR, can be obtained by interchanging the amplifiers in the two cases. It has also been proved that the dc PSR, its dominant frequency breakpoint (where performance starts to degrade), and three subsequent breakpoints are determined by the dc open-loop gain, error amplifier bandwidth, unity-gain frequency (UGF) of the system, output pole, and ESR zero, respectively. These results were verified with SPICE simulations using BSIM3 models for the TSMC 0.35 /spl mu/m CMOS process from MOSIS.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115927356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 194

A high-speed power and resolution adaptive flash analog-to-digital converter 高速功率和分辨率自适应闪存模数转换器

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362342

Sunny Nahata, Kyusun Choi, Jincheol Yoo

引用次数: 14

A 3.8Ghz channel-select filter using 0.18/spl mu/m CMOS 采用0.18/spl mu/m CMOS的3.8Ghz通道选择滤波器

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI: 10.1109/SOCC.2004.1362471

Jiandong Ge, A. Dinh

引用次数: 2