A compensation technique for transistor mismatch in current mirrors

Abstract

A compensation technique to correct the mismatch in the current mirrors due to transistor process parameter variations is presented. The compensation is achieved by varying the drain voltage of the mirroring transistors. This method is implemented by just adding a single transistor, operating in the linear region at the drain of the mirroring transistor. The circuit is simulated for a threshold voltage mismatch of /spl plusmn/10%. The simulation results show that the percentage error in the mirrored currents reduced from 48% to 3% for a threshold voltage mismatch of +10% and from 70% to 10% for a threshold voltage mismatch of -10%, for a wide range of input current values. The affect of temperature on the performance of the circuit is studied. The power consumption with and without the compensation transistor is compared. The compensation technique is successfully implemented in a CMOS image sensor.