A 0.13/spl mu/m 1Gb/s/channel store-and-forward network on-chip

Abstract

A parametric packed-switched scalable network on chip allows energy/throughput/latency tradeoff for data-intensive communication-centric systems. At a clock rate of 200MHz the network guarantees block-free average 1 Gb/s per channel. The test chip includes 64-interfaces network on chip and traffic generators.