2012 14th International Conference on Electronic Materials and Packaging (EMAP)最新文献_第3页

Thin packages enabling thin mobile products 薄封装实现薄移动产品

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507839

William T. Chen, A. Tseng, B. Appelt

引用次数: 1

Solder volume effects on fatigue life of BGA structure Cu/Sn-3.0Ag-0.5Cu/Cu interconnects 焊料体积对BGA结构Cu/Sn-3.0Ag-0.5Cu/Cu互连疲劳寿命的影响

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507908

H. Qin, Xunping Li, Xin-Ping Zhang

引用次数: 2

Color consistence improvement in LED packages 提高LED封装的色彩一致性

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507883

Cell K. Y. Wong, S. Leung, Lin Niu, Gongqi Fan, Xiang Zhou, C. Yuan, Guoqi Zhang, Yanglin Li, Menglong Tu, Shaofang Wang

引用次数: 0

Mechanical fastening to enable room temperature packaging for LOCs based on biocompatible hydrogel thin film 机械紧固，使室温包装的loc基于生物相容性水凝胶薄膜

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507899

Weiwei Zhao, Changqing Liu, C. Lenardi, T. Santaniello, Fengshun Wu

引用次数: 3

Effects of surface treatments on the performance of high thermal conductive die attach adhesives (DAAs) 表面处理对高导热模贴胶性能的影响

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507869

Chenmin Liu, D. Lu, Xianxin Lang, A. Choi, P. W. Lee

{"title":"Effects of surface treatments on the performance of high thermal conductive die attach adhesives (DAAs)","authors":"Chenmin Liu, D. Lu, Xianxin Lang, A. Choi, P. W. Lee","doi":"10.1109/EMAP.2012.6507869","DOIUrl":"https://doi.org/10.1109/EMAP.2012.6507869","url":null,"abstract":"Die attach adhesives (DAAs) do more than attach the die to the die pad, substrate, or cavity. They also provide thermal and/or electrical conductivity between the die and the package, essentially affecting the performance of the device while operating in the field. This study was carried out to investigate the effect of surface treatment on the electrical, thermal as well as mechanical properties of silver nanocomposite epoxy die attach adhesives. Several different types of surfactants, including thiol, silane-based coupling agent, siloxane, etc. were employed for silver filler functionalization and morphological studies have shown noticeable improvement in filler dispersion in the treated composite system compared to those untreated system. The properties of the DAAs and the interaction between the fillers and the polymers were carefully studied using a series of techniques including FTIR, SEM, Thermal conductivity testing system, etc, which showed that the surface treatment can enhance the thermal and electrical conductivity as well as the adhesion of the composite system.","PeriodicalId":182576,"journal":{"name":"2012 14th International Conference on Electronic Materials and Packaging (EMAP)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130620259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A study on evaluation method of new packaging structure for high-temperature power device 高温功率器件新型封装结构评价方法研究

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507918

A. Higuchi, Qiang Yu, Toshikazu Oshidari, Mingliang Cui

引用次数: 0

Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes 3D TSV DRAM封装在制造过程中的翘曲、应力和KOZ

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507849

P. Huang, M. Tsai, C. Y. Huang, P. Lin, Lawrence Huang, Michael Chang, S. Shih, J.P. Lin

{"title":"Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes","authors":"P. Huang, M. Tsai, C. Y. Huang, P. Lin, Lawrence Huang, Michael Chang, S. Shih, J.P. Lin","doi":"10.1109/EMAP.2012.6507849","DOIUrl":"https://doi.org/10.1109/EMAP.2012.6507849","url":null,"abstract":"The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260°C, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moiré is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moiré have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.","PeriodicalId":182576,"journal":{"name":"2012 14th International Conference on Electronic Materials and Packaging (EMAP)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132189478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Anomaly detection for chromaticity shift of high power white LED with mahalanobis distance approach 用马氏距离法检测大功率白光LED色度偏移

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507916

Jiajie Fan, Kam-Chuen Yung, M. Pecht

引用次数: 6

Through Silicon Via (TSV) redundancy - a high reliability, networking product perspective 通过硅孔(TSV)冗余-高可靠性，网络化产品的角度

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507851

Poh Choon Chew, Li Li, Jie Xue, William Eklow

{"title":"Through Silicon Via (TSV) redundancy - a high reliability, networking product perspective","authors":"Poh Choon Chew, Li Li, Jie Xue, William Eklow","doi":"10.1109/EMAP.2012.6507851","DOIUrl":"https://doi.org/10.1109/EMAP.2012.6507851","url":null,"abstract":"3-D, stacked ICs offer a promising solution to speed, power and density requirements, as the industry strives to scale to Moore's Law. Through Silicon Vias (TSV) are integral parts to 3-D stacked ICs. TSVs shorten interconnects between logic elements, thus reducing power while increasing performance. TSVs may comprise a significant portion (both logically and physically) of the 3D die stack. It's likely that tens of thousands of TSVs will be incorporated into a 3D die stack. Even though it's widely considered that the TSV yield will be very high, the large number of TSVs still presents a significant risk, given that it is difficult to have 100% test coverage, and a single TSV failure in the field can invalidate an entire die stack (multiplying yield loss by the number of die in the stack). Reliability of TSVs is not clearly understood yet and can also present significant field issues. TSV redundancy has been proposed as a way to mitigate the risk of TSV failure in the stack. This paper will look at published work on TSV redundancy, as well as standards and practical work. The paper will take a practical perspective, taking into account: cost, design (performance), and implementation/deployment considerations. The paper will conclude by providing guidelines and recommendations, which can be used to develop a TSV redundancy strategy at the device level for high reliability networking applications.","PeriodicalId":182576,"journal":{"name":"2012 14th International Conference on Electronic Materials and Packaging (EMAP)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133562589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Laminates for MEMS and BioMEMS 用于MEMS和BioMEMS的层压板

2012 14th International Conference on Electronic Materials and Packaging (EMAP) Pub Date : 2012-12-01 DOI: 10.1109/EMAP.2012.6507843

M. Bachman, G. Li

引用次数: 0