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2008 IEEE Workshop on Signal Processing Systems最新文献

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Soft decoder architecture of LT codes LT码的软解码器结构
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671764
Kai Zhang, Xinming Huang, Chen Shen
{"title":"Soft decoder architecture of LT codes","authors":"Kai Zhang, Xinming Huang, Chen Shen","doi":"10.1109/SIPS.2008.4671764","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671764","url":null,"abstract":"Luby transform (LT) codes, as the first class of efficient rateless codes, attract a lot of attention in the coding theory field. However, the VLSI implementation of LT codes is challenging due to its random code construction characteristic as well as the flexible output length. In this paper, we present an applicable architecture of a soft-decision LT decoder with a block length of 1024 bits and 100 iterations. Partly parallel input node processing and output node processing techniques are both adopted to accelerate decoding speed. An efficient router and reverse router are designed to indicate the graphic connectivity between input nodes and output nodes. The parallel architecture is prototyped on the target FPGA device.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123312707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low-complexity high-speed 4-D TCM decoder 低复杂度高速4-D TCM解码器
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671765
Jinjin He, Zhongfeng Wang, Huaping Liu
{"title":"Low-complexity high-speed 4-D TCM decoder","authors":"Jinjin He, Zhongfeng Wang, Huaping Liu","doi":"10.1109/SIPS.2008.4671765","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671765","url":null,"abstract":"This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture for the transition metrics unit (TMU) is proposed to significantly reduce the computation complexity without degrading the performance. In addition, pipelining and parallel processing techniques are exploited to increase the decoding throughput. Synthesis results show that the FPGA implementation of the TCM decoder can achieve a maximum throughput of 1.062 Gbps.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defect-tolerant digital filtering with unreliable molecular electronics 不可靠分子电子学的容错数字滤波
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671761
Shuo Wang, Jianwei Dai, Lei Wang
{"title":"Defect-tolerant digital filtering with unreliable molecular electronics","authors":"Shuo Wang, Jianwei Dai, Lei Wang","doi":"10.1109/SIPS.2008.4671761","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671761","url":null,"abstract":"Molecular electronics such as silicon nanowires (NW) and carbon nanotubes (CNT) are considered to be the future computational substrates due to their ultra-high density and superior energy efficiency. However, excessive defects from bottom-up self-assembly fabrication pose a major technological barrier to achieving reliable computing at the molecular scale. Existing solutions targeting absolute correctness introduce high cost and complexity in post-fabrication testing and defect diagnosis. In this paper, we propose a new approach exploiting algorithm level enhancements for defect-insensitive signal processing. By deliberately allowing molecular-scale integrated systems to bear defects, the proposed design framework achieves reliable signal processing while significantly reduces the cost of defect tolerance.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134422663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Two-dimensional crosstalk avoidance codes 二维串扰避免码
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671746
Xuebin Wu, Zhiyuan Yan, Yuan Xie
{"title":"Two-dimensional crosstalk avoidance codes","authors":"Xuebin Wu, Zhiyuan Yan, Yuan Xie","doi":"10.1109/SIPS.2008.4671746","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671746","url":null,"abstract":"Global buses in deep submicron system-on-chip designs suffer from increasing crosstalk delay as the feature size shrinks. As an technology-independent solution, crosstalk avoidance coding alleviates the problem while requiring less area and power than shielding. Most previously considered crosstalk avoidance codes are one-dimensional, and have limited code rates. In this paper, we propose two-dimensional crosstalk avoidance codes (TDCAC), which achieve higher code rate at the expense of longer latency. Specifically, we investigate the maximum code rate for TDCAC with and without memory.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129553568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Efficient ordering schemes for sphere decoder 球面解码器的高效排序方案
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671753
Yongmei Dai, Zhiyuan Yan
{"title":"Efficient ordering schemes for sphere decoder","authors":"Yongmei Dai, Zhiyuan Yan","doi":"10.1109/SIPS.2008.4671753","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671753","url":null,"abstract":"In this paper, we propose an efficient ordering scheme that can be embedded in the QR decomposition to reduce the average and worst-case computational complexity of the sphere decoding (SD) algorithm. Our proposed ordering scheme takes into account both the channel matrix and the received signal (noise), and is designed based on a study of the data collected from worst-case scenarios. Simulation results show that our proposed ordering scheme leads to lower average and worst-case computational complexity for the SD algorithm than the optimal vertical Bell Labs layered space-time (V-BLAST) ordering scheme. We also propose a simplified ordering scheme when the unconstrained zero-forcing (ZF) estimate is unavailable.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116411322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A method for improving the efficiency of a two-level memory hierarchy 一种提高两级内存层次结构效率的方法
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671734
Radomir Jakovljevic, A. Beric
{"title":"A method for improving the efficiency of a two-level memory hierarchy","authors":"Radomir Jakovljevic, A. Beric","doi":"10.1109/SIPS.2008.4671734","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671734","url":null,"abstract":"Video processing applications often use motion estimation and compensation, either to ensure high quality of output pictures in case of post processing or in many video coding standards. In case of the High Definition video format, that is picture resolution of 1920times1080 pixels, the off-chip memory bandwidth requirements are high. The typical answer to those requirements is a two-level memory hierarchy. However, in case of large search area, the on-chip memory bandwidth is still high, which has significant impact to performance and power dissipation. In this paper, we propose a method to reduce the on-chip memory bandwidth, typically by 4 times. As immediate result, performance improves by 50% or power dissipation of the two-level memory hierarchy reduces by 35%. The price for these improvements is either reduced vertical dimension of the search area or increased onchip memory capacity. In both cases the price is moderate, typically 20%.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123821387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DSP implementation of probabilistic sound source localization 概率声源定位的DSP实现
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671763
Seung Seob Yeom, Jong-suk Choi, Y. Lim, Mignon Park
{"title":"DSP implementation of probabilistic sound source localization","authors":"Seung Seob Yeom, Jong-suk Choi, Y. Lim, Mignon Park","doi":"10.1109/SIPS.2008.4671763","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671763","url":null,"abstract":"This paper describes a DSP implementation of probabilistic sound source localization algorithm. Time delay of arrival (TDOA) between two microphones through cross-correlation method has been used for sound localization in our robot platforms. However, since cross-correlation values are highly dependent on the upcoming sound signal and acoustic environment, time delay values and localization results are easily perturbed. Here, probabilistic method for sound source localization is presented. And its DSP implementation is applied to the pan-tilt robot that we developed.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114127693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding framework 视频解码器重新配置和AVS扩展在新的MPEG可重构视频编码框架
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671756
Dandan Ding, Lu Yu, Christophe Lucarz, M. Mattavelli
{"title":"Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding framework","authors":"Dandan Ding, Lu Yu, Christophe Lucarz, M. Mattavelli","doi":"10.1109/SIPS.2008.4671756","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671756","url":null,"abstract":"Multimedia devices are now required to support multiple coding standards. Supporting seamlessly both interoperability between standards and flexibility for application specific optimizations is a great challenge for current video coding technology. After a brief description of the new MPEG reconfigurable video coding (RVC) framework, this paper describes possible decoder reconfigurations within this framework. The essential idea behind this framework is to reuse as most as possible the algorithms or architectures which are common to several different standards and to reconfigure video decoders in a flexible way at the coding tool level. A coding tool is an encapsulated piece of algorithm. Reconfiguration can address specific optimization objectives such as improvement in colour reproduction or higher performance at high bitrate. These simple examples show that the tool level definition of the video tool library is flexible enough to support the incremental introduction of new coding algorithms, the usage of algorithms taken from different video standards (i.e. AVS is provided in one example), and the possibility of high level reconfigurations. Thus, this paper demonstrates that the RVC framework offers a great flexibility in selecting coding tools for decoder reconfigurations to satisfy a wide variety of different applications.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124222532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
New simplified sum-product algorithm for low complexity LDPC decoding 低复杂度LDPC译码的新简化和积算法
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671738
Myung Hun Lee, J. Han, M. Sunwoo
{"title":"New simplified sum-product algorithm for low complexity LDPC decoding","authors":"Myung Hun Lee, J. Han, M. Sunwoo","doi":"10.1109/SIPS.2008.4671738","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671738","url":null,"abstract":"This paper proposes new simplified sum-product (SSP) decoding algorithm to improve BER performance for low-density parity-check codes. The proposed SSP algorithm can replace multiplications and divisions with additions and subtractions without extra computations. In addition, the proposed SSP algorithm can simplify both the ln[tanh(x)] and exp[tanh-1(x)] by using two quantization tables which can reduce tremendous computational complexity. Moreover, the simulation results show that the proposed SSP algorithm can improve about 0.3~0.8 dB of BER performance compared with the existing modified sum-product algorithm.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115174644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Hierarchical run time deadlock detection in process networks 进程网络中的分层运行时死锁检测
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671769
Bin Jiang, E. Deprettere, B. Kienhuis
{"title":"Hierarchical run time deadlock detection in process networks","authors":"Bin Jiang, E. Deprettere, B. Kienhuis","doi":"10.1109/SIPS.2008.4671769","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671769","url":null,"abstract":"Deadlock detection is a well-studied problem that may be considered solved from a theoretical point of view. However, specific cases may demand for specific solutions. One such specific case is deadlock detection in Kahn Process Networks. The Kahn process network (KPN) is an expressive model of computation that is widely used to model and specify deterministic streaming applications. The processes in the network communicate point-to-point over FIFO channels whose sizes are undecidable in general. As a consequence, deadlock may occur and, therefore, a run-time deadlock detection mechanism is required. This can be organized in a centralized way, a distributed way, and a hierarchical way. Centralized and distributed procedures have been reported in the literature. In this paper, we propose a novel hierarchical approach for KPN deadlock detection at run time. We also give results for the implementation on the IBM Cell processor.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128787080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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