2008 IEEE Workshop on Signal Processing Systems最新文献

A highly parallel Turbo Product Code decoder without interleaving resource 一个高度并行Turbo产品码解码器，没有交错资源

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671728

Camille Leroux, C. Jégo, P. Adde, M. Jézéquel, Deepak Gupta

引用次数: 11

Low-complexity polynomials modulo integer with linearly incremented variable 具有线性递增变量的低复杂度多项式模整数

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671771

P. Salmela, H. Sorokin, J. Takala

引用次数: 1

A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels 时序蒙特卡罗均衡器的收缩结构，用于频率选择MIMO信道

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671739

M. Shabany, P. Gulak

引用次数: 0

Efficient mapping of advanced signal processing algorithms on multi-processor architectures 先进的信号处理算法在多处理器架构上的有效映射

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671774

Bhavana B. Manjunath, Aaron S. Williams, C. Chakrabarti, A. Papandreou-Suppappola

{"title":"Efficient mapping of advanced signal processing algorithms on multi-processor architectures","authors":"Bhavana B. Manjunath, Aaron S. Williams, C. Chakrabarti, A. Papandreou-Suppappola","doi":"10.1109/SIPS.2008.4671774","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671774","url":null,"abstract":"Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power performance in every generation. To utilize the potential of such a system, signal processing algorithms have to be efficiently parallelized so that the load can be distributed evenly among the multiple processing units. In this paper, we study several advanced deterministic and stochastic signal processing algorithms and their computation using multiple processing units. Specifically, we consider two commonly used time-frequency signal representations, the short-time Fourier transform and the Wigner distribution, and we demonstrate their parallelization with low communication overhead. We also consider sequential Monte Carlo estimation techniques such as particle filtering, and we demonstrate that its multiple processor implementation requires large data exchanges and thus a high communication overhead. We propose a modified mapping scheme that reduces this overhead at the expense of a slight loss in accuracy, and we evaluate the performance of the scheme for a state estimation problem with respect to accuracy and scalability.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127378034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition CAPTCHA字符识别视觉分割系统的仿生统一模型

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671755

Chi-Wei Lin, Yu-Han Chen, Liang-Gee Chen

引用次数: 12

Parallel channel interleavers for 3GPP2/UMB 用于3GPP2/UMB的并行通道交织器

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671737

Mohammad M. Mansour

{"title":"Parallel channel interleavers for 3GPP2/UMB","authors":"Mohammad M. Mansour","doi":"10.1109/SIPS.2008.4671737","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671737","url":null,"abstract":"The design of efficient parallel pruned channel interleavers for 3GPP2 ultra mobile broadband (UMB) standard is considered. Channel interleaving in UMB is based on a bit-reversal algorithm in which addresses get mapped from linear order into bit-reversed order. To accommodate for variable packet lengths L, interleaving is done using a mother interleaver length of M = 2n, where n is the smallest integer that satisfies L les M, such that outlier interleaved addresses greater than L-1 get pruned away. Pruning creates a serial bottleneck since the interleaved address of a linear address x is now a function of the interleaving operation as well as the number of pruned addresses up to x. A generic parallel lookahead pruned (PLP) interleaving scheme that breaks this dependency is proposed. The efficiency of the proposed scheme is demonstrated in the context of UMB channel interleavers in this paper, and in the context of UMB turbo interleavers in a separate work . An iterative pruned bit-reversal algorithm that interleaves any address in O(log L) steps is presented. A parallel architecture of the proposed algorithm employing simple logic gates and having a short critical path delay is also presented. The proposed algorithm and architecture are valuable in reducing (de-)interleaving latency in emerging wireless standards that employ pruned bit-reversal channel (de-)interleaving in their PHY layer such as UMB.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115518209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study 数据流程序的自动软件合成:一个MPEG-4简单剖面解码器案例研究

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671776

Ghislain Roquier, M. Wipliez, M. Raulet, J. Janneck, Ian D. Miller, D. Parlour

{"title":"Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study","authors":"Ghislain Roquier, M. Wipliez, M. Raulet, J. Janneck, Ian D. Miller, D. Parlour","doi":"10.1109/SIPS.2008.4671776","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671776","url":null,"abstract":"The MPEG reconfigurable video coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified high-level specification of current MPEG video coding technologies. In this framework, a decoder is built as a configuration of video coding modules taken from the standard ldquoMPEG toolbox libraryrdquo. The elements of the library are specified by a textual description that expresses the I/O behavior of each module and by a reference software written using the CAL Actor Language. A decoder configuration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level specification to efficient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model. Experimental results of the RVC Expertpsilas MPEG-4 simple profile decoder synthesis are reported. The generated code and the associated SystemC model are validated against the original CAL description which is simulated using the open dataflow environment.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128323497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 55

On the verification of multi-standard SoC’S for reconfigurable video coding based on algorithm/architecture co-exploration 基于算法/架构协同探索的可重构视频编码多标准SoC的验证

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671757

G. Lee, He-Yuan Lin, Ming-Jiun Wang, Bo-Han Chen, Yuan-Long Cheng

引用次数: 3

High-throughput dual-mode single/double binary map processor design for wireless wan 无线广域网高吞吐量双模单/双二进制地图处理器设计

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671742

Chun-Yu Chen, Cheng-Hung Lin, A. Wu

引用次数: 5

Scheduling of dataflow models within the Reconfigurable Video Coding framework 可重构视频编码框架中数据流模型的调度

2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671759

J. Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, P. Brisk, M. Mattavelli

引用次数: 27