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2008 IEEE Workshop on Signal Processing Systems最新文献

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Reduced-complexity MSGR-based matrix inversion 基于msgr的低复杂度矩阵反演
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671749
Lei Ma, K. Dickson, J. McAllister, J. McCanny, M. Sellathurai
{"title":"Reduced-complexity MSGR-based matrix inversion","authors":"Lei Ma, K. Dickson, J. McAllister, J. McCanny, M. Sellathurai","doi":"10.1109/SIPS.2008.4671749","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671749","url":null,"abstract":"A novel method to significantly reduce the complexity of real-time hardware/software implementations of MSGR-based matrix inversion for MIMO wireless communication systems is presented. It is shown, through extensive simulation of this new technique within a T-BLAST MIMO system, that removing the scale-factor from the MSGR algorithm has no adverse effect on the bit-error rate performance of this practical application. Moreover, this new modification to the MSGR algorithm reduces the number of multiply and divide operations in MSGR-based matrix inversion by 18-19%. Furthermore, it is shown that reduced-precision fixed-point arithmetic may be exploited to further reduce the complexity of the implementation while maintaining acceptable bit-error rate performance.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114525806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Further cost reduction of adaptive echo and next cancellers for high-speed Ethernet transceivers 进一步降低高速以太网收发器的自适应回波和下一个消除器的成本
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671767
Jier Chen, K. Parhi
{"title":"Further cost reduction of adaptive echo and next cancellers for high-speed Ethernet transceivers","authors":"Jier Chen, K. Parhi","doi":"10.1109/SIPS.2008.4671767","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671767","url":null,"abstract":"Efficient implementation of adaptive echo and near end crosstalk (NEXT) cancellers in high-speed Ethernet transceivers continues to be a challenging problem. In our previous work, we proposed a new method based on word-length reduction technique to reduce hardware cost of the filter part in adaptive echo and NEXT cancellers. However, the high hardware cost of the weight update part in these adaptive cancellers was not reduced by the above method. This paper presents a new complexity reduction scheme for the weight update part in adaptive echo and NEXT cancellers. By reducing hardware cost of the weight update part, the overall hardware cost of these cancellers can be further reduced. It is shown that, by applying the proposed scheme to the 10 Gigabit Ethernet over copper (10 GBASE-T) system, the hardware cost of adaptive echo and NEXT cancellers can be reduced by about 42.02% only with 1.5 dB performance loss, compared with the traditional design.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131747136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power efficient dynamic-range utilisation for DSP on FPGA FPGA上DSP的功率高效动态范围利用
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671768
S. McKeown, Roger Francis Woods, J. McAllister
{"title":"Power efficient dynamic-range utilisation for DSP on FPGA","authors":"S. McKeown, Roger Francis Woods, J. McAllister","doi":"10.1109/SIPS.2008.4671768","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671768","url":null,"abstract":"A power and resource efficient dasiadynamic-range utilisationpsila technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data representation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132283614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of belief propagation for hardware realization 硬件实现中的信念传播分析
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671754
Chao-Chung Cheng, Chia-Kai Liang, Yen-Chieh Lai, Homer H. Chen, Liang-Gee Chen
{"title":"Analysis of belief propagation for hardware realization","authors":"Chao-Chung Cheng, Chia-Kai Liang, Yen-Chieh Lai, Homer H. Chen, Liang-Gee Chen","doi":"10.1109/SIPS.2008.4671754","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671754","url":null,"abstract":"Belief propagation has become a popular technique for solving computer vision problems, such as stereo estimation and image denoising. However, it requires large memory and bandwidth, and hence naive hardware implementation is prohibitive. In this paper, we first analyze the memory and bandwidth requirements of the technique from the hardware perspective. Then, we propose a tile-based belief propagation algorithm that works with existing data reuse schemes and achieves bandwidth reduction by a factor of 10 to 400. We apply the proposed algorithm to stereo estimation and show that its performance is comparable to the original algorithm.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121672071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Location-Constrained Particle Filter human positioning and tracking system 位置约束粒子滤波人体定位与跟踪系统
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671740
Chih-Hao Chao, Chun-Yuan Chu, A. Wu
{"title":"Location-Constrained Particle Filter human positioning and tracking system","authors":"Chih-Hao Chao, Chun-Yuan Chu, A. Wu","doi":"10.1109/SIPS.2008.4671740","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671740","url":null,"abstract":"This paper proposes a Location-Constrained Particle Filter (LC-PF) for Radio Signal Strength Indication (RSSI) based indoor localization system. Based on proposed LC-PF, the RSSI fluctuation problem can be restrained. The proposed methods include location-constrained importance weight updating (LC-WU) and location-constrained propagation model (LC-model). LC-WU eliminates particles in prohibited regions based on the geolocation of the map. The LC-model propagates particles based on different turning probabilities in different regions. These two methods can be applied separately or jointly. The proposed LC-PF has 2.48 m average accuracy improvement over basic PF with 68% error reduction, and results in 2.07 m accuracy with 90% confidence.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding 四舍五入误差对LDPC译码中对数和积算法决策的影响
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671745
N. Kanistras, Vassilis Paliouras
{"title":"Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding","authors":"N. Kanistras, Vassilis Paliouras","doi":"10.1109/SIPS.2008.4671745","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671745","url":null,"abstract":"In this paper the impact of the roundoff error on the decisions taken by the log sum-product LDPC decoding algorithm is studied. The mechanism, by means of which roundoff alters the decisions of a finite word length implementation of the algorithm compared to the infinite precision case, is analyzed and a corresponding theoretical model is developed. Experimental results prove the validity of the proposed model.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"2926 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127453046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Parallelization of AdaBoost algorithm on multi-core processors AdaBoost算法在多核处理器上的并行化
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671775
Yen-kuang Chen, Wenlong Li, Xiaofeng Tong
{"title":"Parallelization of AdaBoost algorithm on multi-core processors","authors":"Yen-kuang Chen, Wenlong Li, Xiaofeng Tong","doi":"10.1109/SIPS.2008.4671775","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671775","url":null,"abstract":"This paper examines and extracts the parallelism in the AdaBoost person detection algorithm on multi-core processors. As multi-core processors become pervasive, effectively executing many threads simultaneously is crucial in harnessing the computation power. Although the application exposes many levels of parallelism, none of them delivers a satisfactory scaling performance on newest multi-core processors due to load imbalance and parallel overhead. This paper demonstrates how to analyze the thread-level parallelism, and how to choose appropriate one to utilize current 4-core and 8-core processors. With careful optimization and parallelization, the AdaBoost person detection algorithm can efficiently utilize the power of multi-core processors, and now it is 7 times faster than the serial version.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127038932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Efficient realization of a cal video decoder on a mobile terminal (position paper) 电话视频解码器在移动终端上的高效实现(意见书)
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671758
C. V. Platen, J. Eker
{"title":"Efficient realization of a cal video decoder on a mobile terminal (position paper)","authors":"C. V. Platen, J. Eker","doi":"10.1109/SIPS.2008.4671758","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671758","url":null,"abstract":"Resource utilization is a very central issue in the development of large-volume embedded systems. Increasingly complex execution platforms for embedded multimedia systems challenge the prevailing approach of achieving high utilization by carefully tuned implementations in C and assembly language. The recently started ACTORS project addresses resource utilization by providing appropriate high-level abstractions. Algorithms will be specified in a dataflow programming model. This position paper describes the dataflow compilation subproject within ACTORS, and the plans for a demonstrator in the form of a wireless video player, which will be compiled from a library of dataflow components. We give an account for existing software synthesis techniques and the challenges that anticipate in applying them to complex dataflow models.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126420693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Error-resilient low-power Viterbi decoders via state clustering 基于状态聚类的容错低功耗维特比解码器
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671766
R. Abdallah, Naresh R Shanbhag
{"title":"Error-resilient low-power Viterbi decoders via state clustering","authors":"R. Abdallah, Naresh R Shanbhag","doi":"10.1109/SIPS.2008.4671766","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671766","url":null,"abstract":"Low-power Viterbi decoder (VD) architectures based on the principle of error-resiliency are presented in this paper. Power reduction in the add-compare-select units (ACSUs) of a VD is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). In either case, the data-dependent timing errors which occur whenever a critical path is excited, are corrected via the application of algorithmic noise-tolerance (ANT). The concept of state clustering is employed to develop efficient estimators for error-correction. Power savings achieved in the presence of VOS and process variations are 71% and 62%, respectively, at a loss of 0.8 dB and 0.6 dB in coding gain in a IBM 130 nm CMOS process.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124330397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 μm technology 100MHz实时色调映射处理器，集成了0.13 μm技术的摄影和梯度压缩
2008 IEEE Workshop on Signal Processing Systems Pub Date : 2008-11-17 DOI: 10.1109/SIPS.2008.4671732
C. Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, R. Tsay
{"title":"A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 μm technology","authors":"C. Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, R. Tsay","doi":"10.1109/SIPS.2008.4671732","DOIUrl":"https://doi.org/10.1109/SIPS.2008.4671732","url":null,"abstract":"As the advance of high quality displays such as light-emitting diode (LED), liquid-crystal-display (LCD) or laser TV, the importance of a real-time high dynamic range (HDR) data processing for display devices increases significantly. Many tone mapping algorithms are proposed for rendering HDR images or videos on display screens. The choice of tone mapping algorithm depends on characteristics of displays such as luminance range, contrast ratio and gamma correction. An ideal HDR tone mapping processor should include different types of tone mapping algorithms and be able to select an appropriate one depending on devices and applications. The photographic tone reproduction has lower complexity and better quality among global tone mapping schemes. The gradient compression, a local tone mapping, is known for detail preservation. In this paper, we present an integrated photographic and gradient tone mapping processor that can be configured for different applications. This design that can process 1024 times 768 images at 60 fps runs at 100 MHz clock and consumes core area of 8.1 mm2 under TSMC 0.13 mum technology with 50% improvement in speed and area compared with previous results.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123628666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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