{"title":"无线广域网高吞吐量双模单/双二进制地图处理器设计","authors":"Chun-Yu Chen, Cheng-Hung Lin, A. Wu","doi":"10.1109/SIPS.2008.4671742","DOIUrl":null,"url":null,"abstract":"In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mum CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.","PeriodicalId":173371,"journal":{"name":"2008 IEEE Workshop on Signal Processing Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"High-throughput dual-mode single/double binary map processor design for wireless wan\",\"authors\":\"Chun-Yu Chen, Cheng-Hung Lin, A. Wu\",\"doi\":\"10.1109/SIPS.2008.4671742\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mum CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.\",\"PeriodicalId\":173371,\"journal\":{\"name\":\"2008 IEEE Workshop on Signal Processing Systems\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Workshop on Signal Processing Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2008.4671742\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Workshop on Signal Processing Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2008.4671742","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
在本文中，我们提出了支持单二进制(SB)和双二进制(DB)卷积turbo码的高吞吐量增强型Max-log-MAP处理器的VLSI实现。引入混合窗(HW)和并行窗(PW)相结合的MAP解码，以支持任意帧大小和高吞吐量。在台积电0.13 μ m CMOS制程中实现了1.28 mm2双模(SB/DB) 2PW-1HW MAP处理器，验证了所提出的方法。所提出的MAP处理器可以作为多标准无线广域网平台的硬件加速器，具有低成本、低能耗的特点。
High-throughput dual-mode single/double binary map processor design for wireless wan
In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mum CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.
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