A method for improving the efficiency of a two-level memory hierarchy

Abstract

Video processing applications often use motion estimation and compensation, either to ensure high quality of output pictures in case of post processing or in many video coding standards. In case of the High Definition video format, that is picture resolution of 1920times1080 pixels, the off-chip memory bandwidth requirements are high. The typical answer to those requirements is a two-level memory hierarchy. However, in case of large search area, the on-chip memory bandwidth is still high, which has significant impact to performance and power dissipation. In this paper, we propose a method to reduce the on-chip memory bandwidth, typically by 4 times. As immediate result, performance improves by 50% or power dissipation of the two-level memory hierarchy reduces by 35%. The price for these improvements is either reduced vertical dimension of the search area or increased onchip memory capacity. In both cases the price is moderate, typically 20%.