Xiang Lin, L. Ravi, S. Mocevic, D. Dong, R. Burgos
{"title":"Active Voltage Balancing Embedded Digital Gate Driver for Series-Connected 10 kV SiC MOSFETs","authors":"Xiang Lin, L. Ravi, S. Mocevic, D. Dong, R. Burgos","doi":"10.1109/APEC39645.2020.9124263","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124263","url":null,"abstract":"This paper focuses on series connection of 10 kV SiC MOSFETs which enables higher operation voltage of devices for medium voltage application. To minimize switching losses, active voltage balancing for series-connected 10 kV SiC MOSFETs is implemented instead of passive snubbers. For this purpose, a new gate driver is designed for active voltage balancing of two series-connected 10 kV SiC MOSFETs with the following features: 1) miniaturized 10 kV drain-source voltage measurement unit and its interconnection to gate-driver; 2) Tunable gate signal delay time adjustment unit with 0.25 ns resolution; 3) Rogowski current sensing unit for fault current detection. Based on the developed gate driver, the FPGA-based closed-loop gate signal timing control for active voltage balancing and fault protection of series-connected 10 kV SiC MOSFETs are designed in this paper. The proposed gate driver and active voltage balancing method are validated in a phase-leg test achieving 16 kV total blocking voltage.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. T. Wodajo, M. Elbuluk, Seungdeog Choi, H. Abu-Rub
{"title":"Capacitor Voltage Ripple Reduction of Hybrid Balanced Two-Leg Five-Level Neutral Point Clamped Inverter","authors":"E. T. Wodajo, M. Elbuluk, Seungdeog Choi, H. Abu-Rub","doi":"10.1109/APEC39645.2020.9124222","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124222","url":null,"abstract":"This paper proposes customization for a hybrid balancing scheme to reduce capacitor voltage ripple in a two-leg five-level neutral point clamped inverter. This customization introduces modulation changes in two regions of the hybrid balancing scheme. Following these changes, the active balancing control target options are re-evaluated to better suit the voltage ripple reduction objective. The paper outlines the backgrounds of changes and alternatives regarding the improvisation being adapted. Lastly, the applicability of the improvisations is demonstrated using a comparative Matlab-Simulink simulation of a two-leg five-level transistor clamped inverter under transient and steady-state conditions.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116942079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shen Xu, Qinsong Qian, T. Tao, Limin Yu, Shengli Lu, Weifeng Sun
{"title":"Synchronous Rectification Using Resonant Capacitor Voltage for Secondary Side Resonant Active Clamp Flyback Converter","authors":"Shen Xu, Qinsong Qian, T. Tao, Limin Yu, Shengli Lu, Weifeng Sun","doi":"10.1109/APEC39645.2020.9124421","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124421","url":null,"abstract":"Secondary side resonant active clamp flyback (SSR-ACF) converter is a better candidate than primary side resonant active clamp flyback (PSR-ACF) converter to be used in high frequency small power supply applications. Based on the resonant capacitor voltage in SSR-ACF converter, this paper proposes an accurate synchronous rectification (SR) control method to turn off the synchronous rectifier (SRer) at the right point. Compared with the current widely used SR detecting method, the turn off point of SRer based on the presented method can not be affect by noise or voltage oscillation, and not need complicated sensing circuit. To verify the proposed SR control method, the simulation and experimental results of a 65w 19.5v output SSR-ACF converter are given. The results show that the SRer can be switched off at the right point by the proposed method. Compared with the current widely used SR detecting method, the efficiency in heavy load is improved by 0.3%.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120987451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matthew R. Overlin, Christopher Smith, M. Ilic, J. Kirtley
{"title":"A Workflow for Non-linear Load Parameter Estimation Using a Power-Hardware-in-the-Loop Experimental Testbed","authors":"Matthew R. Overlin, Christopher Smith, M. Ilic, J. Kirtley","doi":"10.1109/APEC39645.2020.9124307","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124307","url":null,"abstract":"Low-inertia microgrids may easily have a single load which can make up most of the total load, thereby greatly affecting stability and power quality. Instead of static load models, dynamic load models are presented here for constant current loads (CILs) and constant power loads (CPLs). Next, a flexible Power-Hardware-in-the-Loop (PHiL) testbed is employed for the experiments in this work. The PHiL testbed consists of a real-time computer working with a power amplifier in order to perturb its voltage and frequency. A connected load serves as the device under test (DUT). Using the captured experimental data as a reference, a parameter estimation algorithm is then implemented. The resulting parameter estimates are used to define simulation models. Both the CIL and CPL dynamic models are simulated to produce waveforms that closely resemble experimental waveforms. The algorithm, referred to as an enhanced monte carlo algorithm (EMCA), is explained in this work. Finally, the EMCA’s resulting parameter estimates are presented.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127474256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A High Frequency CLLLC Bi-directional Series Resonant Converter DAB Using an Integrated PCB Winding Transformer","authors":"Sheng-yang Yu, C. Hsiao, Jack Weng","doi":"10.1109/APEC39645.2020.9124521","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124521","url":null,"abstract":"A unique integrated printed circuit board winding transformer has been proposed in this paper to be used in a high efficiency, high power density capacitor-inductor-inductor-inductor-capacitor series resonant dual active bridge converter (CLLLC-SRes-DAB) and key design considerations for CLLLC-SRes-DAB are addressed. Winding structure, core arrangement of the series inductor and transformer, and the shape of heatsink are carefully designed in order to minimize core volume, transformer intra-winding capacitance (CTX), and eddy current losses caused by fringing flux near air gaps. A 6.6kW CLLLC-SRes-DAB prototype with a 500kHz series resonant frequency has been built to evaluate the performance of the proposed transformer. 98% peak efficiency is achieved in this 6.6kW CLLLC-SRes-DAB design.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126119403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A New Two-Switch PFC DCM Boost Rectifier for Aviation Applications","authors":"T. Sadílek, Misha Kumar, Y. Jang, P. Barbosa","doi":"10.1109/APEC39645.2020.9124406","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124406","url":null,"abstract":"A new two-switch, single-phase, power-factor-correction (PFC), discontinuous-conduction-mode (DCM) boost rectifier that features zero-voltage switching (ZVS) and can achieve less than 5% input-current total harmonic distortion (THD) by injecting a simple feedforward signal obtained from input and output voltages to the output voltage feedback control is introduced. Since low THD is achieved without high bandwidth active current shaping control, the proposed topology is suitable for modern aviation applications that require line frequency up to 800 Hz. The evaluation was performed on a 320 W prototype designed to operate from 94-134 V line input and deliver 220 V dc output. The prototype achieves 2.3% THD at full load over the line frequency range from 360 Hz to 800 Hz and meets the required harmonic limits specified by the DO-160 standard that describes the environmental conditions and test procedures for airborne equipment.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123604201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization of 1200V 300A SiC MOSFET Switching Performance Dependence on Load-Cable -Output Filter and Control Deadtime Optimization","authors":"Yujia Cui, Willy Sedano, Peizhong Yi, Lixiang Wei","doi":"10.1109/APEC39645.2020.9124496","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124496","url":null,"abstract":"SiC MOSFET switching exhibits high dependence on load current, especially during switch-off. Higher dv/dt from SiC faster switching necessitates installation of output filter when long cables are used for inverter-motor connection. Both long cable and dv/dt filter introduce further deviation on switching performance. Impacts from varying load levels, long cable and output filter are investigated experimentally and compared with Si IGBTs performance in this paper. Among the variables, load current demonstrates dominant effect on turn-off time. Based on detailed characterization results, relationship between load current and turn-off time is derived for control deadtime optimization.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122684456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ruthardt, L. Schnabel, Philipp Ziegler, P. Marx, K. Sharma, M. Fischer, M. Nitzsche, J. Roth-Stielow
{"title":"Closed Loop Junction Temperature Control of Power Transistors for Lifetime Extension","authors":"J. Ruthardt, L. Schnabel, Philipp Ziegler, P. Marx, K. Sharma, M. Fischer, M. Nitzsche, J. Roth-Stielow","doi":"10.1109/APEC39645.2020.9124000","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124000","url":null,"abstract":"The lifetime of power transistors significantly depends on the junction temperature swings. These temperature swings occur, for instance when the load conditions of the power electronic circuit change. In this work, a closed loop junction temperature control system is designed to increase the expected lifetime of power transistors. Therefore, the control system reduces the occurring temperature swings by influencing the power losses of the power transistor. For that, the gate driver’s supply voltage is adjusted, which affects the switching speed and the conduction characteristics. The junction temperature is measured by determination of the temperature sensitive internal gate resistance via the high-frequency gate-signalinjection method and fed back to the junction temperature controller. Both, the junction temperature measurement method and the control system are evaluated with a three-phase two-level voltage-source inverter. It is extended by a control strategy, which calculates a suitable set value for the controller in order to reduce junction temperature swings.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122976726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Garry Jean-Pierre, N. Altin, Ahmad El Shafei, A. Nasiri
{"title":"A Control Scheme Based on Lyapunov Function for Cascaded H-Bridge Multilevel Active Rectifiers","authors":"Garry Jean-Pierre, N. Altin, Ahmad El Shafei, A. Nasiri","doi":"10.1109/APEC39645.2020.9124234","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124234","url":null,"abstract":"The cascaded H-bridge multilevel active rectifier is a prominent converter configuration. It presents compelling advantages, including high adjustability for a number of applications, such as in solid-state transformers, traction applications, medium and high power motor drives and battery chargers. However, when the H-bridge is operating under an unbalanced load and asymmetrical voltage conditions, it becomes important to design advanced control strategies to maintain the stability of the system. In this study, a Lyapunov-function based control method is proposed for controlling the single-phase cascaded H-bridge active rectifier to achieve global asymptotic stability. A capacitor voltage feedback is added to the conventional Lyapunov-function based stabilizing control method to minimize the resonance of the LCL filter. Additionally, a Proportional-Resonant (PR) control approach is adopted to obtain the reference current signal. This increases the robustness of the current control scheme. A DC voltage balancing control procedure is also employed to prevent the unbalanced DC voltage conditions among the H-bridges. The DC voltage is controlled via a PI controller. The capability of the control approach is verified with simulation and experimental studies.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Voltage Interpolation Method in Inverter Modeling for Fast Electromagnetic Transient Simulations","authors":"S. Horiuchi, K. Sano, T. Noda","doi":"10.1109/APEC39645.2020.9124494","DOIUrl":"https://doi.org/10.1109/APEC39645.2020.9124494","url":null,"abstract":"The electromagnetic transient (EMT) simulation of a power system involving power-electronics converters requires a fairly small time-step size to take into account switching of converters thus leading to a heavy computational burden. To accelerate such simulations, this paper generalizes the time average method (TAM), originally developed for real-time simulations, so that it becomes suitable to off-line EMT simulations. For obtaining accurate current waveforms with a large time step, the TAM and the proposed method represents each arm of an inverter by a voltage source, and its output voltage is modified by interpolation at an instance of switching. For the interpolation, the proposed method uses the trapezoidal method of integration which is widely-used in off-line simulation programs, while the TAM uses the primitive backward Euler method. In addition, the proposed method uses a simple formula to identify the switching instance for the implementation on off-the-shelf PCs, rather than a hardware counter in an FPGA as used in the TAM. This paper shows that the proposed method reduces computation time by a factor of 15 for the off-line simulation of a single-phase inverter with reasonable reproduction of harmonics.","PeriodicalId":171455,"journal":{"name":"2020 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}