{"title":"Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents","authors":"J. Maiz","doi":"10.1109/RELPHY.1989.36349","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36349","url":null,"abstract":"The electromigration of Al-1%-Si interconnects under bidirectional (BC) and pulsed unidirectional (PDC) signals is discussed. The effect of signal asymmetry, duty cycle and frequency on the damage generation rate has been tested. The data suggests that the equivalent DC current of a non-DC signal is given by the average of the signal current for frequencies 1 kHz and higher. A transition region from an average DC equivalent circuit model to an ON-time equivalent type model has been identified around 1 Hz for PDC signals at 3.3E6 A/cm/sup 2/ and 200 degrees C. The refilling of microvoids under current reversal prevents the observation of that transition region for symmetrical bidirectional currents. PDC signals are shown to behave as particular cases of a generalized bidirectional signal. A physical model of the kinetics of material accumulation/depletion is described to show that a high-frequency operation approximation naturally leads to the average DC equivalent-current model.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123206112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability aspects of laser programmable redundancy: infrared vs. green, polysilicon vs. silicide","authors":"J. Chlipala, L. Scarfone","doi":"10.1109/RELPHY.1989.36339","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36339","url":null,"abstract":"The laser explosion of memory redundancy target links has been simulated and temperature evolution profiles produced. The subsequent analysis suggests the following order starting with the most reliable: (1) polysilicon links with infrared laser; (2a) polysilicon links with green laser; (2b) silicide-polysilicon links with infrared laser; and (3) silicide-polysilicon links with green laser. Lower-melting point silicide (e.g. TiSi/sub 2/) is shown to hold some advantage over high-melting-point silicide (e.g. TaSi/sub 2/) as a target material. This advantage, however, is not enough to elevate it over polysilicon links in the reliability rank order.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"696 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130899875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of the breakdown testing of thermal silicon oxides and the effects of preoxidation surface treatment","authors":"D. Kao, J. M. Delarios, C. R. Helms, B. E. Deal","doi":"10.1109/RELPHY.1989.36310","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36310","url":null,"abstract":"The properties of 175 AA thermal oxides have been studied using three testing methods (constant voltage, constant current, and ramped voltage) under a wide range of stressing conditions, along with wafer level statistics. Thus, the role of stress levels of accelerated testing and the effects of wafer surface treatment could be examined. In particular, a constant charge-to-breakdown Q/sub bd/ at low voltage and current stress levels is identified. The effect of preoxidation surface treatment is investigated using different wafer cleans, deliberate contamination, and other process variables such as dry and wet oxidations.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126740054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bryant, T. Furukawa, J. Mandelman, S. Mittl, W. Noble, E. Nowak, W. Wade, S. Ogura, M. Wordeman
{"title":"Angled implant fully overlapped LDD (AI-FOLD) NFETs for performance and reliability","authors":"A. Bryant, T. Furukawa, J. Mandelman, S. Mittl, W. Noble, E. Nowak, W. Wade, S. Ogura, M. Wordeman","doi":"10.1109/RELPHY.1989.36337","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36337","url":null,"abstract":"Fully overlapped lightly doped drain FOLD n-channel MOSFETs built for the purpose of improving the tradeoff between performance and reliability are discussed. Full gate overlap was achieved by using angled implants to extend LDD (lightly-doped drain) regions beneath the gate edge of devices. The dose and energy of the angled implants were varied. The parasitic overlap capacitance and series resistance as well as the reliability enhancement introduced by the FOLD structure are investigated in detail. The series resistance is shown to be strongly dependent on gate voltage, while the overlap capacitance is found to be reduced significantly by depletion of the FOLD drain regions. The corresponding reduction in hot-carrier-limited channel length more than compensates for the increase in parasitics, indicating substantial enhancement in net drive performance.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128584363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
William J. Fritz, Laura B. Bauer, Clint S. Miller, McDonnell Douglas
{"title":"Analysis of aluminum gallium arsenide laser diodes failing due to nonradiative regions behind the facets","authors":"William J. Fritz, Laura B. Bauer, Clint S. Miller, McDonnell Douglas","doi":"10.1109/RELPHY.1989.36318","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36318","url":null,"abstract":"Reliability studies have established the long life capability of AlGaAs laser diodes (15-25 years) and have identified many failure mechanisms. One failure mechanism in improperly facet-passivated devices is the formation of nonradiative regions behind the facet. To study the dynamics of this process, devices with intentionally uncoated facets were tested. The study indicated that the nonradiative regions behind the facets are probably due to an oxide growth on the facets. The nonradiative regions occurred relatively early in the test and then saturated. The effect on optical power was an initially rapid, but saturable decrease that correlated with nonradiative region growth. The observed saturation time of the nonradiative regions was inversely related to the square of the initial optical power. The authors emphasize the importance of correctly passivating and protecting the facet with coatings to prevent oxidation and the formation of nonradiative regions.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116020715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The impact of wafer back surface finish on chip strength","authors":"T.B. Lim","doi":"10.1109/RELPHY.1989.36334","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36334","url":null,"abstract":"A correlation between the wafer back surface roughness and the resistance of the chip to stress-induced failures is discussed. Chip strength was measured using the simply-supported beam method for chips of different backside roughness. Encapsulated samples were subsequently subjected to mechanical impact loading and thermal stresses as in vapor phase flow. The results show that the chip strength bears an inversely proportional relationship with the roughness of the wafer back. Hence, it is important to control the wafer back surface roughness for reliability improvement, especially for surface mount devices.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133625501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Time dependent dielectric breakdown at 210 AA oxides","authors":"K. Boyko, D. L. Gerlach","doi":"10.1109/RELPHY.1989.36309","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36309","url":null,"abstract":"Time-dependent dielectric breakdown (TDDB) data on 210-AA oxide films made with a 1.25- mu m CMOS process using large-area test capacitors (0.3 cm/sup 2/) are presented. Stress temperatures of 60 degrees C and 150 degrees C were used while the electric field stress was varied from near-operation conditions (3 MV/cm) to highly accelerated conditions (8 MV/cm). Approximately 14000 test capacitors have been aged. In an attempt to model electric field functionality, an abrupt change in the standard deviation (sigma) of the log-normal failure distribution was observed at moderate stress conditions. At high stress conditions, a field dependent activation energy and a temperature-dependent acceleration parameter were observed. However, at low-stress conditions, an activation energy independent of field and an acceleration parameter independent of temperature were observed. The change in the behavior of the sigma, the activation energy, and the acceleration parameter occur at the same stress condition. It is believed that these changes may indicate a change in the physical failure mechanism at moderate stress conditions.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122290409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Nishimura, S. Murata, S. Kuroda, O. Enomoto, H. Kitegawa, S. Hasegawa
{"title":"Long term reliability of SiO/sub 2//SiN/SiO/sub 2/ thin layer insulator formed in 9 mu m deep trench on high boron concentrated silicon","authors":"A. Nishimura, S. Murata, S. Kuroda, O. Enomoto, H. Kitegawa, S. Hasegawa","doi":"10.1109/RELPHY.1989.36338","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36338","url":null,"abstract":"The SiO/sub 2//SiN/SiO/sub 2/ (ONO) capacitor formed in the 9 mu m-deep trench is investigated in terms of leakage current and long-term reliability. The leakage current and time-dependent dielectric breakdown (TDDB) characteristics are comparable for both planar and trench type ONO structures. Therefore the test results are not specific to trench structures only but are common characteristics of ONO films. Breakdown voltage of the ONO film is dependent on gate bias polarity and the ratio of bottom-oxide to top-oxide thicknesses. In general, the current is controlled by the exit-oxide thickness for electron current in the ONO film. The mean time to failure becomes longer as the nitride thickness increases. This characteristic is most prominent in the nitrogen annealed samples. The behavior of electric-field factor beta was investigated for variations in nitride thickness. From these results it is concluded that nitride-dominant ONO film is better for long-term reliability.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114705126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Oxide charge trapping and HCI susceptibility of a submicron CMOS dual-poly (N/sup +//P/sup +/) gate technology","authors":"S. Sun, K. Fu, C. Swift, J. Yeargain","doi":"10.1109/RELPHY.1989.36342","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36342","url":null,"abstract":"Gate-oxide charge trapping and hot-carrier injection (HCI) susceptibility of a submicrometer CMOS dual-poly (n/sup +//p/sup +/) gate, Ti-salicide, double-metal technology are discussed. The Si-SiO/sub 2/ interface property is believed to be modified by the p/sup +/ poly gate process, possibly due to boron penetration from the p/sup +/ polysilicon into the gate oxide. This accounts for the observed reduction in hole trapping during constant-current stress of the p/sup +/ poly gate capacitors and the large critical energy for interface trap generation during HCI stress of the p/sup +/ poly gate transistors. A general empirical relationship between the HCI power law parameters A (the precoefficient) and n (the power index) was obtained for both n-channel p-channel devices to describe the stress-time dependent degradation. Using the derived MOSFET lifetime, the limiting device type for this submicrometer CMOS dual-poly gate technology has also been determined.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115550958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new reliability problem associated with Ar ion sputter cleaning of interconnect vias","authors":"H. Tomioka, S. Tanabe, K. Mizukami","doi":"10.1109/RELPHY.1989.36317","DOIUrl":"https://doi.org/10.1109/RELPHY.1989.36317","url":null,"abstract":"The cleanliness of a sputter-etched surface of an aluminum alloy in interconnect vias has been investigated. In situ Auger analysis of the sputter-etched vias indicates that sputter-etch cleaning prior to metallization removes the natural oxide on the aluminum surface, but leaves a thin insulating layer due to redeposition of the atoms sputtered out of the intermetal dielectric. Existence of the redeposited layer was also confirmed by scanning electron microscopy (SEM) cross-sectional observation of the vias. The redeposited insulating layer causes contact failure of vias during life testing including high-temperature storage and operation. A multipinhole contact model is proposed to explain the failure mechanism.<<ETX>>","PeriodicalId":171192,"journal":{"name":"27th Annual Proceedings., International Reliability Physics Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}