2017 Panhellenic Conference on Electronics and Telecommunications (PACET)最新文献_第3页

A monitoring system for people living with Alzheimer's disease 一个监测阿尔茨海默病患者的系统

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259985

Irene-Maria Tabakis, M. Dasygenis, M. Tsolaki

{"title":"A monitoring system for people living with Alzheimer's disease","authors":"Irene-Maria Tabakis, M. Dasygenis, M. Tsolaki","doi":"10.1109/PACET.2017.8259985","DOIUrl":"https://doi.org/10.1109/PACET.2017.8259985","url":null,"abstract":"Neurodegenerative diseases affect millions of people worldwide, and Alzheimer's disease is one of the most common types. Alzheimer's disease and other dementias have a deep impact not only to those who are diagnosed but also on the people who are close to them and society as a whole. Various researchers and companies have proposed products that aid towards relief for these people. We noticed that there are plenty of products, which are targeting to patients' safety, although there is a gap: there is no link between the products and the needs of caregivers, while at the same time most of the products do not protect sufficiently patient' s personal data. We designed a complete system to monitor and record patient's locations, heart rate and sleep which organizes the way that the caregivers comprehend and satisfy patient's needs. In this paper, we present a monitoring system for people living with Alzheimer's disease. This system consists of a wearable and an Android application. It can be used from every involving actors. Our system developed thanks to the close and constant communication with patients and their caregivers in an outpatient clinic for dementia and memory loss by a team of engineers and doctors. The evaluation results lead to rate the significance of our system.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129424627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Crossbar sector addressing scheme on SRAMs ram上的横杆扇区寻址方案

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259951

Lazaros Spyridopoulos, Nikos Konofaos, Theodoras Simopoulos, G. Alexiou

引用次数: 1

The MapReduce application of matrix multiplication implemented on field programmable gate arrays 矩阵乘法的MapReduce应用在现场可编程门阵列上实现

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259986

Michail-Antisthenis I. Tsompanas, G. Sirakoulis

引用次数: 0

SIMO PPM optical wireless communication system over gamma turbulence channels with generalized pointing errors 具有广义指向误差的湍流信道上的SIMO PPM光学无线通信系统

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259982

M. P. Ninos, H. Nistazakis, G. Tombras, C. Volos

引用次数: 0

A toolset for the design of embedded systems, enabling HW/SW co-simulation, performance optimisation and source code generation 嵌入式系统设计工具集，支持硬件/软件协同仿真、性能优化和源代码生成

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259981

Michael Loupis

引用次数: 0

Real number modeling of a flash ADC using SystemVerilog 利用SystemVerilog实现flash ADC的实数建模

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259969

Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos

引用次数: 12

Realizing virtual output queues in high throughput data center nodes 在高吞吐量数据中心节点中实现虚拟输出队列

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259971

A. Kyriakos, I. Patronas, G. Tzimas, V. Kitsakis, D. Reisis

{"title":"Realizing virtual output queues in high throughput data center nodes","authors":"A. Kyriakos, I. Patronas, G. Tzimas, V. Kitsakis, D. Reisis","doi":"10.1109/PACET.2017.8259971","DOIUrl":"https://doi.org/10.1109/PACET.2017.8259971","url":null,"abstract":"Contemporary Data Center designs involve optical switches and Top-of-Rack (ToR) switches to connect thousands of servers. Most often ToR switches include Virtual Output Queues (VOQs) to alleviate the effect of the head-of-line blocking problem and improve the network's performance. The design of the VOQs has to minimize the latency in frame transmission and to keep the implementation cost, which includes buffers and the organization overhead, at relatively low level. The current paper focuses on a data center operating with Time Division Multiple Access (TDMA) method and presents a VOQ architecture placed at the input of the ToR switch supporting 10GEthernet port. The VOQ architecture consists of a limited number of queues corresponding to the active destinations of each input port, which forward the Ethernet frames to a shared buffer. A low latency efficient mechanism assigns the active destinations to the queues. This work is part of a complete ToR design that is developed with a commercial Ethernet switch, a Xilinx Virtex VC707 and a Xilinx NetFPGA boards. The VOQs are realized and validated on the NetFPGA board.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125204444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Laboratory jitter removal circuit for single-bit all-digital frequency synthesis 用于单比特全数字频率合成的实验室抖动去除电路

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259964

A. Raptakis, Costas Oustoglou, P. Sotiriadis

{"title":"Laboratory jitter removal circuit for single-bit all-digital frequency synthesis","authors":"A. Raptakis, Costas Oustoglou, P. Sotiriadis","doi":"10.1109/PACET.2017.8259964","DOIUrl":"https://doi.org/10.1109/PACET.2017.8259964","url":null,"abstract":"All-digital frequency synthesizers based on sigma-delta modulation with single-bit output can have exceptionally high dynamic range and spurs-free dynamic range, in simulation. The performance of their FPGA implementations however is significantly limited by the jitter introduced by the FPGA and its clock reference, which is translated to phase noise. This paper introduces a laboratory circuit architecture for suppressing the FPGA and reference jitter in order to achieve spectrally cleaner single-bit output sequences and demonstrate the achievable performance of the all-digital frequency synthesizers. The proposed architecture is based on a 1-Bit DAC re-clocking the singlebit digital output of the FPGA using one of the two low-jitter clocks generated by a low phase noise reference oscillator. The second clock is used to clock the FPGA after passing through a programmable delay line and a small-value frequency divider. The implementation of the circuit's architecture is presented discussing the design challenges. Phase noise measurements demonstrate the performance of the circuit. Spectral measurements illustrate the effectiveness of jitter removal in the case of a sigma-delta modulator single-bit output.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127970352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Conductivity distribution measurement at different low frequencies using a modular 64 electrode electrical impedance tomography system 采用模块化64电极电阻抗层析成像系统测量不同低频下的电导率分布

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259973

Christos Dimas, P. Sotiriadis

引用次数: 1

Efficient all-digital frequency synthesizer based on multi-step look-ahead sigma-delta modulation 基于多步前瞻σ - δ调制的高效全数字频率合成器

2017 Panhellenic Conference on Electronics and Telecommunications (PACET) Pub Date : 2017-11-01 DOI: 10.1109/PACET.2017.8259967

Nikos Temenos, Charis Basetas, P. Sotiriadis

引用次数: 0